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HCF40101B PDF预览

HCF40101B

更新时间: 2024-11-03 22:56:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
11页 270K
描述
9-BIT PARITY GENERATOR/CHECKER

HCF40101B 数据手册

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HCC/HCF40101B  
9-BIT PARITY GENERATOR/CHECKER  
.
.
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED AT 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
EY  
F
.
.
(Plastic Package)  
(Ceramic Frit Seal Package)  
C1  
M1  
(Plastic Chip Carrier)  
(Micro Package)  
ORDER CODES :  
HCC40101BF  
HCF40101BM1  
HCF40101BEY  
HCF40101BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC40101B (extended temperature range)  
and HCF40101B (intermediate temperature range)  
are monolithic integrated circuits, available in 14-  
lead dual in-line plastic or ceramic package and  
plastic micro package.  
The HCC/HCF40101B is a 9-bit (8 data bits plus 1  
parity bit) parity generator/checker. It may be used  
to detect errors in data transmission or data retrie-  
val. Odd and even outputs facilitate odd or even  
parity generation and checking. When used as a  
parity generator, a parity bit is supplied along with  
the data to generate an even or odd parity output.  
When used a parity checker, the received data bits  
and parity bits are compared for correct parity. The  
even or odd outputs are used to indicate an error in  
the received data. Word-length capability is expan-  
dable by cascading. The HCC/HCF40101B is also  
provided with an inhibit control. If the inhibit control  
is set at logical 1”, the even and odd outputs go to  
a logical ”0”.  
June 1989  
1/11  

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