Datasheet > HCF40103

HCF40103

更新时间： 2024-11-03 23:54:55

品牌	Logo	应用领域
其他 - ETC		计数器
页数	文件大小	规格书
14页	831K
描述
8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

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中文翻译

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数据手册

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HCF40103 数据手册

HCF40103B

8-STAGE PRESETTABLE SYNCHRONOUS

8 BIT BINARY DOWN COUNTERS

■

SYNCHRONOUS OR ASYNCHRONOUS

PRESET

MEDIUM -SPEED OPERATION :

=3.6MHz (Typ.) at V = 10V

■

CASCADABLE

QUIESCENT CURRENT SPECIF. UP TO 20V

5V, 10V AND 15V PARAMETRIC RATINGS

INPUT LEAKAGE CURRENT

DIP

SOP

I = 100nA (MAX) AT V = 18V T = 25°C

ORDER CODES

PACKAGE

■

100% TESTED FOR QUIESCENT CURRENT

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

TUBE

T & R

DIP

HCF40103BEY

HCF40103BM1

SOP

HCF40103M013TR

CE) input is high. The CARRY-OUT/ZERO

DETECT (CO/ZD) output goes low when the

count reaches zero if the CI/CE input is low, and

remains low for one full clock period. When the

SYNCHRONOUS PRESET ENABLE (SPE) input

is low, data at the JAM input is clocked into the

counter on the next positive clock transition

regardless of the state of the CI/CE input. When

the ASYNCHRONOUS PRESET ENABLE (APE)

input is low, data at the JAM inputs is

asynchronously forced into the counter regardless

of the state of the SPE, CI/CE, or CLOCK inputs.

JAM inputs J0-J7 represent a single 8 bit binary

word. When the CLEAR (CLR) input is low, the

counter is asynchronously cleared to its maximum

DESCRIPTION

HCF40103B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.

HCF40103B consists of an 8-stage synchronous

down counter with a single output that is active

when the internal count is zero. This device

contains a single 8-bit binary counter. It has

control inputs for enabling or disabling the clock,

for clearing the counter to its maximum count, and

for presetting the counter either synchronously or

asynchronously. All control inputs and the

CARRY-OUT/ZERO

DETECT

output

are

active-low logics. In normal operation, the counter

is decremented by one count on each positive

transition of the CLOCK. Counting is inhibited

when the CARRY-IN/COUNTER ENABLE (CI/

count (255 ) regardless of the state of any other

input. The precedent relationship between control

input is indicated in the truth table. If all control

PIN CONNECTION

September 2002

1/14

12 3 4 5 6 7...14

中文翻译

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与HCF40103相关器件

型号	品牌	获取价格	描述	数据表
HCF40103B	STMICROELECTRONICS	获取价格	8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
HCF40103B_02	STMICROELECTRONICS	获取价格	8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS
HCF40103BC1	ETC	获取价格	Synchronous Down Counter
HCF40103BEY	STMICROELECTRONICS	获取价格	8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS
HCF40103BF	ETC	获取价格	Synchronous Down Counter
HCF40103BM1	STMICROELECTRONICS	获取价格	8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS
HCF40103M013TR	STMICROELECTRONICS	获取价格	8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS
HCF40104	STMICROELECTRONICS	获取价格	4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
HCF40104B	STMICROELECTRONICS	获取价格	4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
HCF40104BC1	STMICROELECTRONICS	获取价格	4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

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