GTLP6C816

更新时间： 2024-11-20 22:20:15

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		时钟驱动器
页数	文件大小	规格书
7页	48K
描述
GTLP-to-TTL 1:6 Clock Driver

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数据手册

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GTLP6C816 数据手册

June 1998

Revised October 1998

GTLP6C816

GTLP-to-TTL 1:6 Clock Driver

typically less than 0.5V, the output level HIGH is 1.5V and

the receiver threshold is 1.0V.

General Description

The GTLP6C816 is a clock driver that provides TTL to

GTLP signal level translation (and vice versa). The device

provides a high speed interface between cards operating at

TTL logic levels and a backplane operating at GTLP logic

levels. High speed backplane operation is a direct result of

GTLP’s reduced output swing (<1V), reduced input thresh-

old levels and output edge rate control. The edge rate con-

Features

■ Interface between TTL and GTLP logic levels

■ Edge Rate Control to minimize noise on the GTLP port

■ Power up/down high impedance for live insertion

■ 1:6 fanout clock driver for TTL port

trol minimizes bus settling time. GTLP is

a Fairchild

■ 1:2 fanout clock driver for GTLP port

Semiconductor derivative of the Gunning Transceiver logic

(GTL) JEDEC standard JESD8-3.

■ TTL compatible driver and control inputs

Fairchild’s GTLP has internal edge-rate control and is pro-

cess, voltage, and temperature (PVT) compensated. Its

function is similar to BTL and GTL but with different output

levels and receiver threshold. GTLP output LOW level is

■ Flow through pinout optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

■ Recommended Operating Temperature −40°C to +85°C

Ordering Code:

Order Number

Package Number Package Description

GTLP6C816MTC MTC24

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Descriptions

Connection Diagram

Pin Names

Description

TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)

OEB

Output Enable (Active LOW)

GTLP Port (TTL Levels)

OEA

Output Enable (Active LOW)

TTL Port (TTL Levels)

V_CCT.GNDT

V_CC

TTL Output Supplies (5V)

Internal Circuitry V_CC(5V)

OBn GTLP Output Grounds

Voltage Reference Input

GNDG

V_REF

OA0–OA5

OB0–OB1

TTL Buffered Clock Outputs

GTLP Buffered Clock Outputs

DS500129.prf

www.fairchildsemi.com

12 3 4 5 6 7

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