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GTLPH16927

更新时间： 2024-11-21 03:40:03
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件时钟
页数 文件大小 规格书
19页 361K
描述
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS

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GTLPH16927 数据手册

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SN74GTLPH16927  
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER  
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS  
SCES413 – OCTOBER 2002  
DGG OR DGV PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
TI-OPC Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
DIR  
OE  
A1  
GND  
A2  
A3  
FSTA  
BIAS V  
B1  
GND  
B2  
2
CC  
OEC Circuitry Improves Signal Integrity  
and Reduces Electromagnetic Interference  
3
4
Bidirectional Interface Between GTLP  
Signal Levels and LVTTL Logic Levels  
5
6
B3  
7
V
V
GTLP Buffered SYSCLK Signal (SSCLK) for  
Source-Synchronous Applications  
CC  
REF  
8
A4  
A5  
A6  
GND  
A7  
B4  
B5  
B6  
GND  
B7  
9
LVTTL Interfaces Are 5-V Tolerant  
Medium-Drive GTLP Outputs (50 mA)  
LVTTL Outputs (–24 mA/24 mA)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GTLP Rise and Fall Times Designed for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
A8  
A9  
B8  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
CMS  
B16  
B17  
GND  
B18  
SSCLK  
I
, Power-Up 3-State, and BIAS V  
CC  
off  
Support Live Insertion  
Bus Hold on A-Port Data Inputs  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
A16  
A17  
GND  
A18  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
CLKOUT  
CKOE  
SYSCLK  
description/ordering information  
The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer.  
Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous  
and clock-synchronous applications. Source-synchronous applications require the skew between the clock  
output and data output to be minimized for optimum maximum-frequency system performance. In order to  
reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a  
predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the  
device.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
PACKAGE  
TSSOP – DGG  
A
Tape and reel  
Tape and reel  
Tape and reel  
SN74GTLPH16927GR  
SN74GTLPH16927VR  
SN74GTLPH16927KR  
GTLPH16927  
GL927  
–40°C to 85°C TVSOP – DGV  
VFBGA – GQL  
GL927  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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