GS9000CCPJ

更新时间： 2024-01-03 11:26:38

品牌	Logo	应用领域
GENNUM		解码器
页数	文件大小	规格书
8页	110K
描述
Serial Digital Decoder

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GS9000CCPJ 数据手册

(MSB)

SWF

HSYNC PD9 PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

SDI

SCI

SS1

SS0

SSC

GS9000C

TOP VIEW

SCE SWC PCLK PD0

(LSB)

Fig. 1 GS9000C Pin Outs, 28 Pin PLCC Package

GS9000C PIN DESCRIPTIONS

PIN NO.

SYMBOL

TYPE

DESCRIPTION

HSYNC

Output

Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected.

Power Supply. Most negative power supply connection.

SWF

Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the

preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the

SWC input.

Power Supply. Most negative power supply connection.

5,6

SDI/SDI

SCI/SCI

SS1/SS0

Inputs

Output

Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.0V

for operation up to 370MHz. See AC Electrical Characteristics Table for details.

7,8

Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.0V

for operation up to 370MHz. See AC Electrical Characteristics Table for details.

9,10

Standard Select Outputs. CMOS (TTL compatible) outputs used with the GS9005A Receiver in

order to perform an automatic standards select function. These outputs are generated by a 2

bit internal binary counter which stops cycling when there is no CARRIER present at the

GS9005A Receiver input or when a valid TRS is detected by the GS9000C.

SSC

Input

Standards Select Control. Analog input used to set a time constant for the standards select hunt

period. An external RC sets the time constant. When a GS9005A Receiver is used, the open

collector CARRIER DETECT output also connects to this pin in order to enable or disable the

internal 2 bit binary counter which controls the hunting process.

Power Supply. Most positive power supply connection.

SCE

Input

SyncCorrectionEnable. ActivehighCMOSinputwhichenablessynccorrectionbynotresetting

the GS9000C’s internal parallel timing on the first sync error. If the next incoming sync is in error,

internal parallel timing will be reset. This is to guard against spurious HSYNC errors. When SCE

is low, a valid sync will always reset the GS9000C’s parallel timing generator.

522 - 49 - 01

1 234 5 6 7 8

下载PDF

与GS9000CCPJ相关器件

型号	品牌	描述	获取价格	数据表
GS9000CCPJE3	GENNUM	Consumer Circuit, CMOS, PQCC28	获取价格
GS9000CCTJ	GENNUM	Serial Digital Decoder	获取价格
GS9000CCTJE3	GENNUM	Consumer Circuit, CMOS, PQCC28	获取价格
GS9000-CPJ	ETC	SMPTE	获取价格
GS9000D	GENNUM	GENLINX II -TM GS9000D Serial Digital Decoder	获取价格
GS9000DCPJ	GENNUM	GENLINX II -TM GS9000D Serial Digital Decoder	获取价格