GS9000C

更新时间： 2024-02-25 17:19:48

品牌	Logo	应用领域
GENNUM		解码器
页数	文件大小	规格书
8页	110K
描述
Serial Digital Decoder

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技术参数
数据手册

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GS9000C 技术参数

生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQCC-J28
功能数量：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子位置：	QUAD	Base Number Matches：	1

GS9000C 数据手册

** Locate the three 0.10µF decoupling

capacitors as close as possible to the

corresponding pins on the GS9000C.

Chip capacitors are recommended.

+5V

22µ

3 x 100n

HSYNC OUTPUT

13 18

HSYNC

PD0

DD DD DD

PARALLEL DATA BIT 0

PARALLEL DATA BIT 1

PARALLEL DATA BIT 2

PARALLEL DATA BIT 3

PARALLEL DATA BIT 4

PARALLEL DATA BIT 5

PARALLEL DATA BIT 6

PARALLEL DATA BIT 7

PARALLEL DATA BIT 8

PARALLEL DATA BIT 9

PARALLEL CLOCK OUT

SYNC CORRECTION ENABLE

DECODER

GS9000C

PDI

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PCLK

SCE

SDI

SCI

SS1

SS0

SSC

SDI

SCI

STANDARDS SELECT BIT 1

STANDARDS SELECT BIT 0

+5V

100k

820p

SWC SWF

SS SS SS

26 15

10p

SYNC WARNING FLAG

13 x 425Ω

39k

All resistors in ohms,

all capacitors in farads,

unless otherwise specified.

+5V

Fig. 8 GS9000C Test Set-Up

4ƒ

DATA

STREAM

With correctly synchronized serial data and clock connected

totheGS9000C, theHSYNCoutput(pin1)willtoggleforeach

HSYNC detected. The Parallel Data bits PD0 through PD9

along with the Parallel Clock can be observed on an

oscilloscope or fed to a logic analyzer. These outputs can

alsobefedthroughasuitableTTLtoECLconvertertodirectly

drive parallel inputs to receiving equipment such as monitors

or digital to analog converters.

ACTIVE VIDEO

& H BLANKING

ACTIVE VIDEO

& H BLANKING

HSYNC

OUT

4:2:2

DATA

STREAM

ACTIVE

VIDEO

BLNK

In operation, the HSYNC output from the GS9000C decoder

toggles on each occurrence of the timing reference signal

(TRS). The state of the HSYNC output is not significant, just

the time at which it toggles.

HSYNC

OUT

Fig. 9 Operation of HSYNC Output

The HSYNC output toggles to indicate the presence of the

TRS on the falling edge of PCLK, one data symbol prior to the

output of the first word in the TRS. In the following diagram,

data is indicated in 10 bit Hex.

PCLK

XXX 3FF 000 000 XXX

PDN

HSYNC

Fig. 10 Operation of HSYNC with Respect to PCLK

522 - 49 - 01

1...3 4 567 8

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