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GS880Z18CGT-250IVT PDF预览

GS880Z18CGT-250IVT

更新时间： 2024-11-30 21:14:35
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
23页 336K
描述
ZBT SRAM, 512KX18, CMOS, ROHS COMPLIANT, TQFP-100

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GS880Z18CGT-250IVT 技术参数

生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.32
其他特性：PIPELINED ARCHITECTURE, FLOW-THROUGH, IT ALSO OPERATES WITH 2.5V SUPPLYJESD-30 代码：R-XQFP-G100
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
封装主体材料：UNSPECIFIED封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

GS880Z18CGT-250IVT 数据手册

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GS880Z18/32/36CT-xxxIV  
250 MHz–150 MHz  
9Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
100-Pin TQFP  
Industrial Temp  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
rail for proper operation. Asynchronous inputs include the  
Features  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V or 2.5 V +10%/–10% core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 2M, 4M, and 18M devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
The GS880Z18/32/36CT-xxxIV may be configured by the  
user to operate in Pipeline or Flow Through mode. Operating  
as a pipelined synchronous device, meaning that in addition to  
the rising edge triggered registers that capture input signals, the  
device incorporates a rising-edge-triggered output register. For  
read cycles, pipelined SRAM output data is temporarily stored  
by the edge triggered output register during the access cycle  
and then released to the output drivers at the next rising edge of  
clock.  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
Functional Description  
The GS880Z18/32/36CT-xxxIV is a 9Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS880Z18/32/36CT-xxxIV is implemented with GSI's  
high performance CMOS technology and is available in a  
JEDEC-standard 100-pin TQFP package.  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
Parameter Synopsis  
-250I  
-200I  
-150I  
Unit  
tKQ  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
195  
220  
170  
185  
145  
165  
mA  
mA  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
155  
175  
135  
160  
133  
145  
mA  
mA  
Rev: 1.04 6/2012  
1/23  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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