Datasheet > GS880Z18-V

GS880Z18-V

更新时间： 2024-11-18 03:10:23

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
24页	993K
描述
9Mb Pipelined and Flow Through Synchronous NBT SRAM

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中文翻译

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GS880Z18-V 数据手册

GS880Z18/32/36BT-xxxV

250 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

9Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

The GS880Z18/32/36BT-xxxV may be configured by the user

to operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS880Z18/32/36BT-xxxV is a 9Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS880Z18/32/36BT-xxxV is implemented with GSI's

high performance CMOS technology and is available in a

JEDEC-standard 100-pin TQFP package.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

Paramter Synopsis

-250

-200

-150

Unit

t_KQ

3.0

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

200

230

170

195

140

160

t_KQ

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

160

185

140

160

128

145

Rev: 1.03 6/2006

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS880Z18-V相关器件

型号	品牌	获取价格	描述	数据表
GS880Z32BGT-150IV	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z32BGT-150IVT	GSI	获取价格	ZBT SRAM, 256KX32, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880Z32BGT-150T	GSI	获取价格	暂无描述
GS880Z32BGT-150V	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z32BGT-200IV	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z32BGT-200IVT	GSI	获取价格	ZBT SRAM, 256KX32, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880Z32BGT-200V	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z32BGT-200VT	GSI	获取价格	ZBT SRAM, 256KX32, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880Z32BGT-250IV	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z32BGT-250IVT	GSI	获取价格	ZBT SRAM, 256KX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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