Datasheet > GS880Z32CGT-150I

GS880Z32CGT-150I

更新时间： 2024-11-22 13:48:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
24页	357K
描述
100 TQFP

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GS880Z32CGT-150I 数据手册

GS880Z18/32/36CT-xxxI

333 MHz–150 MHz

9Mb Pipelined and Flow Through

Synchronous NBT SRAM

100-Pin TQFP

Industrial Temp

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

rail for proper operation. Asynchronous inputs include the

Features

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

The GS880Z18/32/36CT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS880Z18/32/36CT is a 9Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS880Z18/32/36CT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

Parameter Synopsis

-333I

-300I

-250I

-200I

-150I

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

260

300

245

280

215

245

190

215

160

180

t_KQ

4.5

5.0

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

200

225

185

210

180

200

160

180

148

165

Rev: 1.04 7/2012

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS880Z32CGT-150I相关器件

型号	品牌	获取价格	描述	数据表
GS880Z32CGT-150IV	GSI	获取价格	100 TQFP
GS880Z32CGT-150V	GSI	获取价格	100 TQFP
GS880Z32CGT-200	GSI	获取价格	100 TQFP
GS880Z32CGT-200I	GSI	获取价格	100 TQFP
GS880Z32CGT-200IV	GSI	获取价格	100 TQFP
GS880Z32CGT-200V	GSI	获取价格	100 TQFP
GS880Z32CGT-250	GSI	获取价格	100 TQFP
GS880Z32CGT-250I	GSI	获取价格	100 TQFP
GS880Z32CGT-250IV	GSI	获取价格	100 TQFP
GS880Z32CGT-250V	GSI	获取价格	100 TQFP

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