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GS880Z18T-80 PDF预览

GS880Z18T-80

更新时间： 2024-11-18 07:02:11
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
25页 406K
描述
8Mb Pipelined and Flow Through Synchronous NBT SRAMs

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GS880Z18T-80 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.77最长访问时间：14 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：66.6 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.19 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS880Z18T-80 数据手册

 浏览型号GS880Z18T-80的Datasheet PDF文件第2页浏览型号GS880Z18T-80的Datasheet PDF文件第3页浏览型号GS880Z18T-80的Datasheet PDF文件第4页浏览型号GS880Z18T-80的Datasheet PDF文件第5页浏览型号GS880Z18T-80的Datasheet PDF文件第6页浏览型号GS880Z18T-80的Datasheet PDF文件第7页 
Preliminary  
GS880Z18/36T-11/100/80/66  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
100 MHz–66 MHz  
3.3 V VDD  
2.5 V and 3.3 V VDDQ  
8Mb Pipelined and Flow Through  
Synchronous NBT SRAMs  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
Features  
• 512K x 18 and 256K x 36 configurations  
• User configurable Pipeline and Flow Through mode  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization  
• Fully pin compatible with both pipelined and flow through  
NtRAM™, NoBL™ and ZBT™ SRAMs  
• Pin compatible with 2M, 4M and 16M (future) devices  
• 3.3 V +10%/–5% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleave Burst mode  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• Clock Control, registered address, data, and control  
• ZZ Pin for automatic power-down  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• JEDEC-standard 100-lead TQFP package  
The GS880Z18/36T may be configured by the user to operate  
in Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, in addition to the rising-edge-triggered  
registers that capture input signals, the device incorporates a  
rising-edge-triggered output register. For read cycles, pipelined  
SRAM output data is temporarily stored by the edge triggered  
output register during the access cycle and then released to the  
output drivers at the next rising edge of clock.  
-11  
-100  
-80  
-66  
tCycle  
tKQ  
IDD  
10 ns  
4.5 ns  
10 ns  
4.5 ns  
12.5 ns  
4.8 ns  
15 ns  
5 ns  
Pipeline  
3-1-1-1  
210 mA 210 mA 190 mA 170 mA  
tKQ  
tCycle  
IDD  
11 ns  
15 ns  
12 ns  
15 ns  
14 ns  
15 ns  
18 ns  
20 ns  
Flow Through  
2-1-1-1  
150 mA 150 mA 130 mA 130 mA  
The GS880Z18/36T is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 100-pin TQFP package.  
Functional Description  
The GS880Z18/36T is an 8Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles  
Clock  
Address  
A
R
B
C
R
D
E
R
F
Read/Write  
W
W
W
Flow Through  
Data I/O  
QA  
DB  
QC  
DD  
QE  
DD  
Pipelined  
Data I/O  
QA  
DB  
QC  
QE  
Rev: 1.10 8/2000  
1/25  
© 1998, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.  
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