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GS88037CT-300T PDF预览

GS88037CT-300T

更新时间： 2024-09-20 13:31:55
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
20页 296K
描述
Cache SRAM, 256KX36, 2.2ns, CMOS, PQFP100, TQFP-100

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中文翻译

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GS88037CT-300T 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.63Is Samacsys：N
最长访问时间：2.2 ns其他特性：PIPELINED ARCHITECTURE, IT ALSO OPERATES WITH 3 V TO 3.6 V SUPPLY
最大时钟频率 (fCLK)：300 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.025 A最小待机电流：2.3 V
子类别：SRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS88037CT-300T 数据手册

 浏览型号GS88037CT-300T的Datasheet PDF文件第2页浏览型号GS88037CT-300T的Datasheet PDF文件第3页浏览型号GS88037CT-300T的Datasheet PDF文件第4页浏览型号GS88037CT-300T的Datasheet PDF文件第5页浏览型号GS88037CT-300T的Datasheet PDF文件第6页浏览型号GS88037CT-300T的Datasheet PDF文件第7页 
GS88037CT-xxx  
333 MHz–200 MHz  
256K x 36  
9Mb Sync Burst SRAM  
100-Pin TQFP  
Commercial Temp  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Burst mode, subsequent burst addresses are generated  
Features  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
• Single Cycle Deselect (SCD) operation  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
SCD Pipelined Reads  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• Ro-HS-compliant 100-lead TQFP package available  
The GS88037CT is a SCD (Single Cycle Deselect) pipelined  
synchronous SRAM. DCD (Dual Cycle Deselect) versions are  
also available. SCD SRAMs pipeline deselect commands one  
stage less than read commands. SCD RAMs begin turning off  
their outputs immediately after the deselect command has been  
captured in the input registers.  
Functional Description  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Applications  
The GS88037CT is a 9,437,184-bit (8,388,608-bit for x32  
version) high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Core and Interface Voltages  
The GS88037CT operates on a 2.5 V or 3.3 V power supply.  
All input are 3.3 V and 2.5 V compatible. Separate output  
power (V  
) pins are used to decouple output noise from the  
DDQ  
internal circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-333  
-300  
-250  
-200  
Unit  
Pipeline  
3-1-1-1  
t
2.0  
3.0  
2.2  
3.3  
2.3  
4.0  
2.7  
5.0  
ns  
ns  
KQ  
tCycle  
Curr (x36)  
280  
260  
225  
195  
mA  
Rev: 1.04 7/2012  
1/20  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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