5秒后页面跳转
捷配首页

Datasheet > GS88036T-11
GS88036T-11 PDF预览

GS88036T-11

更新时间： 2024-11-08 02:58:47
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
25页 1033K
描述
512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs

阅读下载

中文翻译

获取价格

GS88036T-11 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.7
最长访问时间：11 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.225 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS88036T-11 数据手册

 浏览型号GS88036T-11的Datasheet PDF文件第2页浏览型号GS88036T-11的Datasheet PDF文件第3页浏览型号GS88036T-11的Datasheet PDF文件第4页浏览型号GS88036T-11的Datasheet PDF文件第5页浏览型号GS88036T-11的Datasheet PDF文件第6页浏览型号GS88036T-11的Datasheet PDF文件第7页 
Preliminary  
GS88018/32/36T-11/11.5/100/80/66  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
100 MHz–66 MHz  
512K x 18, 256K x 32, 256K x 36  
8Mb Sync Burst SRAMs  
3.3 V V  
DD  
3.3 V and 2.5 V I/O  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipelined  
operation  
• Single Cycle Deselect (SCD) operation  
• 3.3 V +10%/–5% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipelined mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Common data inputs and data outputs  
• Clock Control, registered, address, data, and control  
• Internal self-timed write cycle  
Flow Through/Pipeline Reads  
The function of the Data Output Register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
SCD Pipelined Reads  
The GS88018/32/36T is a SCD (Single Cycle Deselect)  
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)  
versions are also available. SCD SRAMs pipeline deselect  
commands one stage less than read commands. SCD RAMs  
begin turning off their outputs immediately after the deselect  
command has been captured in the input registers.  
• Automatic power-down for portable applications  
• 100-lead TQFP package  
-11  
-11.5  
-100  
10 ns 12.5 ns 15 ns  
5 ns  
225 mA 225 mA 225 mA 200 mA 185 mA  
-80  
-66  
Pipeline tCycle 10 ns  
10 ns  
Byte Write and Global Write  
3-1-1-1  
tKQ  
IDD  
4.0 ns 4.0 ns 4.0 ns 4.5 ns  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Flow  
Through  
2-1-1-1  
tKQ  
tCycle  
IDD  
11 ns 11.5 ns 12 ns  
15 ns 15 ns 15 ns  
180 mA 180 mA 180 mA 175 mA 165 mA  
14 ns  
15 ns  
18 ns  
20 ns  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Functional Description  
Applications  
Core and Interface Voltages  
The GS88018/32/36T is a 9,437,184-bit (8,388,608-bit for x32  
version) high performance synchronous SRAM with a 2-bit  
burst address counter. Although of a type originally developed  
for Level 2 Cache applications supporting high performance  
CPUs, the device now finds application in synchronous SRAM  
applications, ranging from DSP main store to networking chip  
set support.  
The GS88018/32/36T operates on a 3.3 V power supply and all  
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate  
output power (VDDQ) pins are used to decouple output noise  
from the internal circuit.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
Rev: 1.11 8/2000  
1/25  
© 2000, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...25

中文翻译

下载PDF

与GS88036T-11相关器件

型号 品牌 获取价格 描述 数据表
GS88036T-11.5 GSI

获取价格

 		Cache SRAM, 256KX36, 11.5ns, CMOS, PQFP100, TQFP-100
GS88036T--11.5 GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
GS88036T--11.5I GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
GS88036T-11.5IT GSI

获取价格

 		Cache SRAM, 256KX36, 11.5ns, CMOS, PQFP100, TQFP-100
GS88036T-11.5T GSI

获取价格

 		Cache SRAM, 256KX36, 11.5ns, CMOS, PQFP100, TQFP-100
GS88036T-11I GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
GS88036T-80 GSI

获取价格

 		512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
GS88036T-80T GSI

获取价格

 		暂无描述
GS88036TT-11.5 GSI

获取价格

 		Standard SRAM, 256KX36, 11.5ns, CMOS, PQFP100
GS88036TT-11.5I GSI

获取价格

 		Standard SRAM, 256KX36, 11.5ns, CMOS, PQFP100

与GS88036T-11相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证