Datasheet > GS8672T18AGE-250IT

GS8672T18AGE-250IT

更新时间： 2024-11-23 14:35:35

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
29页	1003K
描述
DDR SRAM, 4MX18, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS8672T18AGE-250IT 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	4MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	SERIAL
认证状态：	Not Qualified	座面最大高度：	1.5 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	15 mm
Base Number Matches：	1

GS8672T18AGE-250IT 数据手册

浏览型号GS8672T18AGE-250IT的Datasheet PDF文件第2页

浏览型号GS8672T18AGE-250IT的Datasheet PDF文件第3页

浏览型号GS8672T18AGE-250IT的Datasheet PDF文件第4页

浏览型号GS8672T18AGE-250IT的Datasheet PDF文件第5页

浏览型号GS8672T18AGE-250IT的Datasheet PDF文件第6页

浏览型号GS8672T18AGE-250IT的Datasheet PDF文件第7页

Preliminary

GS8672T18/36AE-333/300/250/200

333 MHz–200 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II™

Burst of 2 ECCRAM™

1.8 V V

1.8 V and 1.5 V

DDQ

Features

Clocking and Addressing Schemes

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 144Mb

devices

The GS8672T18/36AE SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaDDR-II ECCRAMs always

transfer data in two packets. When a new address is loaded, A0

presets an internal 1-bit address counter. The counter

increments by 1 (toggles) for each beat of a burst of two data

transfer.

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

On-Chip Error Correction Code

SigmaDDR™ Family Overview

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

The GS8672T18/36AE SigmaDDR-II ECCRAMs are built in

compliance with the SigmaDDR-II SRAM pinout standard for

Common I/O synchronous SRAMs. They are 75,497,472-bit

(72Mb) SRAMs. The GS8672T18/36AE SigmaDDR-II

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02 5/2010

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...29

中文翻译

下载PDF

与GS8672T18AGE-250IT相关器件

型号	品牌	获取价格	描述	数据表
GS8672T18AGE-333	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165
GS8672T18AGE-333I	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165
GS8672T18AGE-333IT	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165
GS8672T18BE-300I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, FBGA-165
GS8672T18BE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, FBGA-165
GS8672T19AE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-333	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-375I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-375IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-375T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

与GS8672T18AGE-250IT相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

35
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

27
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

55
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

52

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672T18AGE-250IT

GS8672T18AGE-250IT 技术参数

GS8672T18AGE-250IT 数据手册

与GS8672T18AGE-250IT相关器件

与GS8672T18AGE-250IT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672T18AGE-250IT

GS8672T18AGE-250IT 技术参数

GS8672T18AGE-250IT 数据手册

与GS8672T18AGE-250IT相关器件

与GS8672T18AGE-250IT相关文章

您还可以找

您在本页遇到什么问题？