Datasheet > GS8672T18BE-300IT

GS8672T18BE-300IT

更新时间： 2024-11-19 15:33:27

品牌	Logo	应用领域
GSI		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
29页	390K
描述
DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, FBGA-165

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GS8672T18BE-300IT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.43	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE, LATE WRITE	最大时钟频率 (fCLK)：	300 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
长度：	17 mm	内存密度：	75497472 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.5 mm	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.91 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm	Base Number Matches：	1

GS8672T18BE-300IT 数据手册

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GS8672T18/36BE-400/333/300/250/200

400 MHz–200 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II™

Burst of 2 ECCRAM™

1.8 V V

1.8 V and 1.5 V

DDQ

C clock inputs. C and C are also independent single-ended

Features

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 18Mb, 36Mb and 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Each internal read and write operation in a SigmaDDR-II B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed.

When a new address is loaded into the part, A0 is used to

initialize the pointers that control the data multiplexer / de-

multiplexer so the ECCRAM can perform "critical word first"

operations. From an external address point of view, regardless

of the starting point, the data transfers always follow the same

sequence {0, 1} or {1, 0} (where the digits shown represent

A0).

SigmaDDR™ ECCRAM Overview

The GS8672T18/36BE SigmaDDR-II ECCRAMs are built in

compliance with the SigmaDDR-II SRAM pinout standard for

Common I/O synchronous SRAMs. They are 75,497,472-bit

(72Mb) SRAMs. The GS8672T18/36BE SigmaDDR-II

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

Clocking and Addressing Schemes

The GS8672T18/36BE SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-400

2.5 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02 1/2013

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...29

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与GS8672T18BE-300IT相关器件

型号	品牌	获取价格	描述	数据表
GS8672T19AE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-333	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-375I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-375IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-375T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-400	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-400I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-400IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AE-400T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T19AGE-300	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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