Datasheet > GS8672T19AE-400T

GS8672T19AE-400T

更新时间： 2024-11-23 14:42:23

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
28页	967K
描述
DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS8672T19AE-400T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE, LATE WRITE
JESD-30 代码：	R-PBGA-B165	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.5 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

GS8672T19AE-400T 数据手册

Preliminary

GS8672T19/37AE-400/375/333/300

72Mb SigmaDDR-II+^TM

Burst of 2 ECCRAM^TM

400 MHz–300 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V and 1.5 V I/O

Features

Clocking and Addressing Schemes

• On-Chip ECC with virtually zero SER

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

The GS8672T19/37AE SigmaDDR-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and future

144Mb devices

Common I/O x36 and x18 SigmaDDR-II+ B2 RAMs always

transfer data in two packets. When a new address is loaded, A0

presets an internal 1 bit address counter. The counter

increments by 1 (toggles) for each beat of a burst of two data

transfer. Because the LSB is tied off internally, the address

field of a SigmaDDR-II+ B2 RAM is always one address pin

less than the advertised index depth (e.g., the 4M x 18 has a

2M addressable index).

On-Chip Error Correction Code

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

SigmaDDR™ ECCRAM Overview

The GS8672T19/37AE ECCRAMs are built in compliance

with the SigmaDDR-II+ SRAM pinout standard for Common

I/O synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672T19/37AE SigmaCIO ECCRAMs are

just one element in a family of low power, low voltage HSTL

I/O ECCRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-400

2.5 ns

0.45 ns

-375

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

tKHKH

tKHQV

2.66 ns

0.45 ns

Rev: 1.00 5/2010

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

中文翻译

下载PDF

与GS8672T19AE-400T相关器件

型号	品牌	获取价格	描述	数据表
GS8672T19AGE-300	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-300I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-300T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-333	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-333I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-333IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-375	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-375I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T19AGE-400	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

与GS8672T19AE-400T相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

36
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

28
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

56
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

53

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672T19AE-400T

GS8672T19AE-400T 技术参数

GS8672T19AE-400T 数据手册

与GS8672T19AE-400T相关器件

与GS8672T19AE-400T相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672T19AE-400T

GS8672T19AE-400T 技术参数

GS8672T19AE-400T 数据手册

与GS8672T19AE-400T相关器件

与GS8672T19AE-400T相关文章

您还可以找

您在本页遇到什么问题？