Datasheet > GS8672T20AE-500T

GS8672T20AE-500T

更新时间： 2024-11-20 09:12:19

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
28页	982K
描述
Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165

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GS8672T20AE-500T 数据手册

Preliminary

GS8672T20/38AE-550/500/450/400

550 MHz–400 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II+

Burst of 2 ECCRAM^TM

1.8 V V

1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.5 Clock Latency

The GS8672T20/38AE SigmaDDR-II+ SRAMs are

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• JEDEC-standard package

• Double Data Rate interface

• Byte Write capability

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with future 144Mb and 288Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Because Common I/O SigmaDDR-II+ ECCRAMs always

transfer data in two packets, A0 is internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfer. Because the LSB is tied off internally, the

address field of a SigmaDDR-II+ B2 RAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

SigmaDDR™ Family Overview

The GS8672T20/38AE SigmaDDR-II+ ECCRAMs are built in

compliance with the SigmaDDR-II+ SRAM pinout standard

for Common I/O synchronous SRAMs. They are

75,497,472-bit (72Mb) SRAMs. The GS8672T20/38AE

SigmaDDR SRAMs are just one element in a family of low

power, low voltage HSTL I/O SRAMs designed to operate at

the speeds needed to implement economical high performance

networking systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-550

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

tKHKH

tKHQV

1.81 ns

0.45 ns

Rev: 1.00 5/2010

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

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与GS8672T20AE-500T相关器件

型号	品牌	获取价格	描述	数据表
GS8672T20AE-550IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672T20AGE-400IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-400T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-450	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-450IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-500	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-500I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-500IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-500T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672T20AGE-550IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA

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