Datasheet > GS8672D38AE-500T

GS8672D38AE-500T

更新时间： 2024-11-07 07:48:39

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
30页	812K
描述
Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165

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GS8672D38AE-500T 数据手册

GS8672D20/38AE-550/500/450/400

72Mb SigmaQuad^TM-II+

Burst of 4 ECCRAM^TM

550 MHz–400 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.5 Clock Latency

The GS8672D20/38AE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 144Mb and future 288Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 4M x 18 has a 1M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

SigmaQuad™ ECCRAM Overview

The GS8672D20/38AE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672D20/38AE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-550

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45ns

-400

2.5 ns

0.45 ns

tKHKH

tKHQV

1.81 ns

0.45ns

Rev: 1.00 5/2010

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...30

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与GS8672D38AE-500T相关器件

型号	品牌	获取价格	描述	数据表
GS8672D38AE-550	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672D38AE-550IT	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672D38BE-400I	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 4 ECCRAMTM
GS8672D38BE-500I	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 4 ECCRAMTM
GS8672D38BE-550I	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 4 ECCRAMTM
GS8672D38BE-633I	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 4 ECCRAMTM
GS8672D38BGE-400	GSI	获取价格	72Mb SigmaQuad-IITM72Mb SigmaQuad-IITM
GS8672D38BGE-400I	GSI	获取价格	JEDEC-standard package
GS8672D38BGE-500I	GSI	获取价格	JEDEC-standard package
GS8672D38BGE-550	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 4 ECCRAMTM

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