Datasheet > 存储 > SRAM> GS8672Q18AE-300T

GS8672Q18AE-300T

更新时间： 2024-11-07 09:04:31

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
27页	813K
描述
Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FBGA-165

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GS8672Q18AE-300T 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.5 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	15 mm
Base Number Matches：	1

GS8672Q18AE-300T 数据手册

Preliminary

GS8672Q18/36AE-333/300/250/200

333 MHz–200 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaQuad-II™

Burst of 2 ECCRAM™

1.8 V V

1.8 V and 1.5 V I/O

Features

Clocking and Addressing Schemes

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

144Mb devices

The GS8672Q18/36AE SigmaQuad-II ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

High, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B2 ΕCCRAMs always

transfer data in two packets, A0 is internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfer. Because the LSB is tied off internally, the

address field of a SigmaQuad-II B2 ECCRAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2048K addressable index).

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ ECCRAM Overview

The GS8672Q18/36AE SigmaQuad-II ECCRAMs are built in

compliance with the SigmaQuad-II SRAM pinout standard for

Separate I/O synchronous SRAMs. They are 75,497,472-bit

(72Mb) ECCRAMs. The GS8672Q18/36AE SigmaQuad-II

ECCRAMs are just one element in a family of Low power,

Low voltage HSTL I/O ECCRAMs designed to operate at the

speeds needed to implement economical High performance

networking systems.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02 5/2010

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...27

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与GS8672Q18AE-300T相关器件

型号	品牌	获取价格	描述	数据表
GS8672Q18AE-333	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FBGA-165
GS8672Q18AE-333I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FBGA-165
GS8672Q18AE-333IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FBGA-165
GS8672Q18AE-333T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FBGA-165
GS8672Q18AGE-200I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-
GS8672Q18AGE-200IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-
GS8672Q18AGE-250	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-
GS8672Q18AGE-300I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-
GS8672Q18AGE-300T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-
GS8672Q18AGE-333IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-

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