Datasheet > 存储 > SRAM> GS8672Q18AGE-333IT

GS8672Q18AGE-333IT

更新时间： 2024-11-07 05:28:11

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
27页	813K
描述
Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GS8672Q18AGE-333IT 数据手册

浏览型号GS8672Q18AGE-333IT的Datasheet PDF文件第2页

浏览型号GS8672Q18AGE-333IT的Datasheet PDF文件第3页

浏览型号GS8672Q18AGE-333IT的Datasheet PDF文件第4页

浏览型号GS8672Q18AGE-333IT的Datasheet PDF文件第5页

浏览型号GS8672Q18AGE-333IT的Datasheet PDF文件第6页

浏览型号GS8672Q18AGE-333IT的Datasheet PDF文件第7页

Preliminary

GS8672Q18/36AE-333/300/250/200

333 MHz–200 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaQuad-II™

Burst of 2 ECCRAM™

1.8 V V

1.8 V and 1.5 V I/O

Features

Clocking and Addressing Schemes

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

144Mb devices

The GS8672Q18/36AE SigmaQuad-II ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

High, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B2 ΕCCRAMs always

transfer data in two packets, A0 is internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfer. Because the LSB is tied off internally, the

address field of a SigmaQuad-II B2 ECCRAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2048K addressable index).

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ ECCRAM Overview

The GS8672Q18/36AE SigmaQuad-II ECCRAMs are built in

compliance with the SigmaQuad-II SRAM pinout standard for

Separate I/O synchronous SRAMs. They are 75,497,472-bit

(72Mb) ECCRAMs. The GS8672Q18/36AE SigmaQuad-II

ECCRAMs are just one element in a family of Low power,

Low voltage HSTL I/O ECCRAMs designed to operate at the

speeds needed to implement economical High performance

networking systems.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02 5/2010

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...27

中文翻译

下载PDF

与GS8672Q18AGE-333IT相关器件

型号	品牌	获取价格	描述	数据表
GS8672Q18AGE-333T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-
GS8672Q18BE-250IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672Q18BE-250T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672Q18BGE-200I	GSI	获取价格	72Mb SigmaQuad-IIâ¢ Burst of 2 ECCRAMâ¢
GS8672Q18BGE-300	GSI	获取价格	72Mb SigmaQuad-II Burst of 2 ECCRAM
GS8672Q19AE-300I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672Q19AE-300IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672Q19AE-300T	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672Q19AE-375IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165
GS8672Q19AE-400I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165

与GS8672Q18AGE-333IT相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672Q18AGE-333IT

GS8672Q18AGE-333IT 数据手册

与GS8672Q18AGE-333IT相关器件

与GS8672Q18AGE-333IT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672Q18AGE-333IT

GS8672Q18AGE-333IT 数据手册

与GS8672Q18AGE-333IT相关器件

与GS8672Q18AGE-333IT相关文章

您还可以找

您在本页遇到什么问题？