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GS8672D38BGE-550I PDF预览

GS8672D38BGE-550I

更新时间: 2024-11-07 00:43:51
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
30页 483K
描述
72Mb SigmaQuad-IITM Burst of 4 ECCRAMTM

GS8672D38BGE-550I 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LBGA, BGA165,11X15,40Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BFactory Lead Time:12 weeks
风险等级:5.82最长访问时间:0.45 ns
最大时钟频率 (fCLK):550 MHzI/O 类型:SEPARATE
JESD-30 代码:R-PBGA-B165长度:17 mm
内存密度:75497472 bit内存集成电路类型:STANDARD SRAM
内存宽度:36功能数量:1
端子数量:165字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.5,1.8 V
认证状态:Not Qualified座面最大高度:1.5 mm
最小待机电流:1.7 V子类别:SRAMs
最大压摆率:2.46 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm

GS8672D38BGE-550I 数据手册

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GS8672D20/38BE-633/550/500/450/400  
72Mb SigmaQuad-II+TM  
Burst of 4 ECCRAMTM  
633 MHz–400 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.5 V I/O  
Features  
Clocking and Addressing Schemes  
• 2.5 Clock Latency  
The GS8672D20/38BE SigmaQuad-II+ ECCRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
• On-Chip ECC with virtually zero SER  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard package  
• Dual Double Data Rate interface  
• Byte Write Capability  
• Burst of 4 Read and Write  
• On-Die Termination (ODT) on Data (D), Byte Write (BW),  
and Clock (K, K) outputs  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with 36Mb and144Mb devices  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Each internal read and write operation in a SigmaQuad-II+ B4  
ECCRAM is four times wider than the device I/O bus. An  
input data bus de-multiplexer is used to accumulate incoming  
data before it is simultaneously written to the memory array.  
An output data multiplexer is used to capture the data produced  
from a single memory array read and then route it to the  
appropriate output drivers as needed. Therefore the address  
field of a SigmaQuad-II+ B4 ECCRAM is always two address  
pins less than the advertised index depth (e.g., the 4M x18 has  
a 1M addressable index).  
On-Chip Error Correction Code  
GSI's ECCRAMs implement an ECC algorithm that detects  
and corrects all single-bit memory errors, including those  
induced by Soft Error Rate (SER) events such as cosmic rays,  
alpha particles. The resulting SER of these devices is  
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude  
improvement over comparable SRAMs with no On-Chip ECC,  
which typically have an SER of 200 FITs/Mb or more. SER  
quoted above is based on reading taken at sea level.  
SigmaQuadECCRAM Overview  
The GS8672D20/38BE are built in compliance with the  
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O  
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)  
ECCRAMs. The GS8672D20/38BE SigmaQuad ECCRAMs  
are just one element in a family of low power, low voltage  
HSTL I/O ECCRAMs designed to operate at the speeds needed  
to implement economical high performance networking  
systems.  
However, the On-Chip Error Correction (ECC) will be  
disabled if a “Half Write” operation is initiated. See the Byte  
Write Contol section for further information.  
Parameter Synopsis  
-633  
-550  
1.81 ns  
0.45 ns  
-500  
2.0 ns  
0.45 ns  
-450  
2.2 ns  
0.45 ns  
-400  
2.5 ns  
0.45 ns  
tKHKH  
tKHQV  
1.57 ns  
0.45 ns  
Rev: 1.03c 8/2017  
1/30  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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