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GS8662S09E-250I PDF预览

GS8662S09E-250I

更新时间: 2024-11-05 05:10:51
品牌 Logo 应用领域
GSI 静态存储器双倍数据速率
页数 文件大小 规格书
37页 1767K
描述
72Mb Burst of 2 DDR SigmaSIO-II SRAM

GS8662S09E-250I 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:165
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.79
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165长度:17 mm
内存密度:75497472 bit内存集成电路类型:DDR SRAM
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:165
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8MX9
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15 mmBase Number Matches:1

GS8662S09E-250I 数据手册

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Preliminary  
GS8662S08/09/18/36E-333/300/250/200/167  
333 MHz–167 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
72Mb Burst of 2  
DDR SigmaSIO-II SRAM  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
• Simultaneous Read and Write SigmaSIO™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• DLL circuitry for wide output data valid window and future  
frequency scaling  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ mode pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with future 144Mb devices  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Bottom View  
165-Bump, 15 mm x 17 mm BGA  
1 mm Bump Pitch, 11 x 15 Bump Array  
JEDEC Std. MO-216, Variation CAB-1  
SigmaRAMFamily Overview  
Clocking and Addressing Schemes  
GS8662S08/09/18/36 are built in compliance with the  
SigmaSIO-II SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. These are the first in a family of wide, very low  
voltage HSTL I/O SRAMs designed to operate at the speeds  
needed to implement economical high performance  
networking systems.  
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It  
employs dual input register clock inputs, K and K. The device  
also allows the user to manipulate the output register clock  
input quasi independently with dual output register clock  
inputs, C and C. If the C clocks are tied high, the K clocks are  
routed internally to fire the output registers instead. Each Burst  
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,  
CQ and CQ, which are synchronized with read data output.  
When used in a source synchronous clocking scheme, the Echo  
Clock outputs can be used to fire input registers at the data’s  
destination.  
Because Separate I/O Burst of 2 RAMs always transfer data in  
two packets, A0 is internally set to 0 for the first read or write  
transfer, and automatically incremented by 1 for the next  
transfer. Because the LSB is tied off internally, the address  
field of a Burst of 2 RAM is always one address pin less than  
the advertised index depth (e.g., the 4M x 18 has a 1M  
addressable index).  
Parameter Synopsis  
- 333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
-250  
4.0 ns  
0.45 ns  
-200  
5.0 ns  
0.45 ns  
-167  
tKHKH  
tKHQV  
6.0 ns  
0.5 ns  
0.45 ns  
Rev: 1.01 9/2005  
1/37  
© 2005, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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