Datasheet > GS8662S09GE-333

GS8662S09GE-333

更新时间： 2024-11-06 05:10:51

品牌	Logo	应用领域
GSI		静态存储器双倍数据速率
页数	文件大小	规格书
37页	1767K
描述
72Mb Burst of 2 DDR SigmaSIO-II SRAM

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中文翻译

获取价格

数据手册

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GS8662S09GE-333 数据手册

Preliminary

GS8662S08/09/18/36E-333/300/250/200/167

333 MHz–167 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb Burst of 2

DDR SigmaSIO-II SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

JEDEC Std. MO-216, Variation CAB-1

SigmaRAM™ Family Overview

Clocking and Addressing Schemes

GS8662S08/09/18/36 are built in compliance with the

SigmaSIO-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It

employs dual input register clock inputs, K and K. The device

also allows the user to manipulate the output register clock

input quasi independently with dual output register clock

inputs, C and C. If the C clocks are tied high, the K clocks are

routed internally to fire the output registers instead. Each Burst

of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,

CQ and CQ, which are synchronized with read data output.

When used in a source synchronous clocking scheme, the Echo

Clock outputs can be used to fire input registers at the data’s

destination.

Because Separate I/O Burst of 2 RAMs always transfer data in

two packets, A0 is internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a Burst of 2 RAM is always one address pin less than

the advertised index depth (e.g., the 4M x 18 has a 1M

addressable index).

Parameter Synopsis

- 333

3.0 ns

0.45 ns

-300

3.3 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

tKHKH

tKHQV

6.0 ns

0.5 ns

0.45 ns

Rev: 1.01 9/2005

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...37

中文翻译

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与GS8662S09GE-333相关器件

型号	品牌	获取价格	描述	数据表
GS8662S09GE-333I	GSI	获取价格	72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S09GE-333IT	GSI	获取价格	DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1
GS8662S09GE-333T	GSI	获取价格	DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1
GS8662S18BD-167	GSI	获取价格	Standard SRAM, 4MX18, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165
GS8662S18BD-200I	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-16
GS8662S18BD-250	GSI	获取价格	165 BGA
GS8662S18BD-250I	GSI	获取价格	165 BGA
GS8662S18BD-300	GSI	获取价格	165 BGA
GS8662S18BD-300I	GSI	获取价格	165 BGA
GS8662S18BD-300IT	GSI	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-16

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