Datasheet > 存储 > SRAM> GS8662R18GE-250I

GS8662R18GE-250I

更新时间： 2024-11-02 05:10:51

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器双倍数据速率
页数	文件大小	规格书
37页	1816K
描述
72Mb SigmaCIO DDR-II Burst of 4 SRAM

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS8662R18GE-250I 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	针数：	165
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.71
Is Samacsys：	N	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.5 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

GS8662R18GE-250I 数据手册

Preliminary

GS8662R08/09/18/36E-333/300/250/200/167

333 MHz–167 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaCIO DDR-II

Burst of 4 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and future

144Mb devices

Bottom View

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

The GS8662R08/09/18/36E are built in compliance with the

SigmaCIO DDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs

always transfer data in four packets. When a new address is

loaded, A0 and A1 preset an internal 2 bit linear address

counter. The counter increments by 1 for each beat of a burst of

four data transfer. The counter always wraps to 00 after

reaching 11, no matter where it starts.

Clocking and Addressing Schemes

The GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer

data in four packets. When a new address is loaded, the LSBs

are internally set to 0 for the first read or write transfer, and

incremented by 1 for the next 3 transfers. Because the LSBs

are tied off internally, the address field of a x8 SigmaCIO

DDR-II B4 RAM is always two address pins less than the

advertised index depth (e.g., the 4M x 18 has a 1024K

addressable index).

Parameter Synopsis

-333

-300

3.3 ns

-250

4.0 ns

-200

-167

tKHKH

tKHQV

3.0 ns

5.0 ns

6.0 ns

0.5 ns

0.45 ns 0.45 ns 0.45 ns 0.45 ns

Rev: 1.01 9/2005

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...37

中文翻译

下载PDF

与GS8662R18GE-250I相关器件

型号	品牌	获取价格	描述	数据表
GS8662R18GE-250IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1
GS8662R18GE-300	GSI	获取价格	72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R18GE-300I	GSI	获取价格	72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R18GE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1
GS8662R18GE-333	GSI	获取价格	72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R18GE-333I	GSI	获取价格	72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R18GE-333IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1
GS8662R18GE-333T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 MM X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1
GS8662R36BD-167T	GSI	获取价格	Standard SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, FPBGA-165
GS8662R36BD-200I	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, FPBGA-165

与GS8662R18GE-250I相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

5
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8662R18GE-250I

GS8662R18GE-250I 技术参数

GS8662R18GE-250I 数据手册

与GS8662R18GE-250I相关器件

与GS8662R18GE-250I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8662R18GE-250I

GS8662R18GE-250I 技术参数

GS8662R18GE-250I 数据手册

与GS8662R18GE-250I相关器件

与GS8662R18GE-250I相关文章

您还可以找

您在本页遇到什么问题？