Datasheet > GS8662R36BD-300

GS8662R36BD-300

更新时间： 2024-11-03 13:48:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
35页	1209K
描述
165 BGA

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GS8662R36BD-300 数据手册

GS8662R08/09/18/36BD-400/350/333/300/250

400 MHz–250 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II^TM

Burst of 4 SRAM

1.8 V V

1.8 V and 1.5 V I/O

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Features

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36, x18 and x9) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Each internal read and write operation in a SigmaDDR-II B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed.

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb

devices

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

When a new address is loaded into a x18 or x36 version of the

part, A0 and A1 are used to initialize the pointers that control

the data multiplexer / de-multiplexer so the RAM can perform

"critical word first" operations. From an external address point

of view, regardless of the starting point, the data transfers

always follow the same linear sequence {00, 01, 10, 11} or

{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where

the digits shown represent A1, A0).

SigmaDDR™ Family Overview

The GS8662R08/09/18/36BD are built in compliance with the

SigmaDDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662R08/09/18/36BD SigmaDDR-II SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Unlike the x18 and x36 versions, the input and output data

multiplexers of the x8 and x9 versions are not preset by

address inputs and therefore do not allow "critical word first"

operations. The address fields of the x8 and x9 SigmaDDR-II

B4 RAMs are two address pins less than the advertised index

depth (e.g., the 8M x 8 has a 2M addressable index, and A0 and

A1 are not accessible address pins).

Clocking and Addressing Schemes

The GS8662R08/09/18/36BD SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

Parameter Synopsis

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02c 12/2011

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

中文翻译

下载PDF

与GS8662R36BD-300相关器件

型号	品牌	获取价格	描述	数据表
GS8662R36BD-300I	GSI	获取价格	165 BGA
GS8662R36BD-333	GSI	获取价格	165 BGA
GS8662R36BD-333I	GSI	获取价格	165 BGA
GS8662R36BD-400	GSI	获取价格	165 BGA
GS8662R36BD-400I	GSI	获取价格	165 BGA
GS8662R36BD-400IT	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, BGA-165
GS8662R36BD-400T	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, BGA-165
GS8662R36BGD-167I	GSI	获取价格	Standard SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-
GS8662R36BGD-167IT	GSI	获取价格	Standard SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-
GS8662R36BGD-167T	GSI	获取价格	Standard SRAM, 2MX36, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-

与GS8662R36BD-300相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

5
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8662R36BD-300

GS8662R36BD-300 数据手册

与GS8662R36BD-300相关器件

与GS8662R36BD-300相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8662R36BD-300

GS8662R36BD-300 数据手册

与GS8662R36BD-300相关器件

与GS8662R36BD-300相关文章

您还可以找

您在本页遇到什么问题？