Datasheet > GS8662R36BD-200I

GS8662R36BD-200I

更新时间： 2024-11-03 09:13:59

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
37页	1317K
描述
Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, FPBGA-165

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GS8662R36BD-200I 数据手册

Preliminary

GS8662R08/09/18/36BD-400/350/333/300/250

400 MHz–250 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II^TM

Burst of 4 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36, x18 and x9) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb

devices

Bottom View

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaDDR™ Family Overview

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

The GS8662R08/09/18/36BD are built in compliance with the

SigmaDDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662R08/09/18/36BD SigmaDDR-II SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Common I/O x36 and x18 SigmaDDR-II B4 RAMs always

transfer data in four packets. When a new address is loaded, A0

and A1 preset an internal 2 bit linear address counter. The

counter increments by 1 for each beat of a burst of four data

transfer. The counter always wraps to 00 after reaching 11, no

matter where it starts.

Clocking and Addressing Schemes

The GS8662R08/09/18/36BD SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Common I/O x8 and x9 SigmaDDR-II B4 RAMs always

transfer data in four packets. When a new address is loaded,

the LSBs are internally set to 0 for the first read or write

transfer, and incremented by 1 for the next 3 transfers.

Because the LSBs are tied off internally, the address field of a

x8/x9 SigmaDDR-II B4 RAM is always two address pins less

than the advertised index depth (e.g., the 8M x 8 has a 2M

addressable index).

Parameter Synopsis

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.01 11/2010

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...37

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与GS8662R36BD-200I相关器件

型号	品牌	获取价格	描述	数据表
GS8662R36BD-200T	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, FPBGA-165
GS8662R36BD-250	GSI	获取价格	165 BGA
GS8662R36BD-250I	GSI	获取价格	165 BGA
GS8662R36BD-300	GSI	获取价格	165 BGA
GS8662R36BD-300I	GSI	获取价格	165 BGA
GS8662R36BD-333	GSI	获取价格	165 BGA
GS8662R36BD-333I	GSI	获取价格	165 BGA
GS8662R36BD-400	GSI	获取价格	165 BGA
GS8662R36BD-400I	GSI	获取价格	165 BGA
GS8662R36BD-400IT	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, BGA-165

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