Datasheet > 存储 > SRAM> GS8640E18GT-167V

GS8640E18GT-167V

更新时间： 2024-09-16 04:56:23

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器
页数	文件大小	规格书
23页	982K
描述
4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs

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GS8640E18GT-167V 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	Factory Lead Time：	8 weeks
风险等级：	5.41	Is Samacsys：	N
最长访问时间：	8 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	75497472 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS8640E18GT-167V 数据手册

Preliminary

GS8640E18/32/36T-xxxV

250 MHz–167 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

4M x 18, 2M x 32, 2M x 36

72Mb Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Dual Cycle Deselect (DCD) operation

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

The GS8640E18/32/36T-xxxV is a DCD (Dual Cycle

Deselect) pipelined synchronous SRAM. SCD (Single Cycle

Deselect) versions are also available. DCD SRAMs pipeline

disable commands to the same degree as read commands. DCD

RAMs hold the deselect command for one full cycle and then

begin turning off their outputs just after the second rising edge

of clock.

Functional Description

Applications

The GS8640E18/32/36T-xxxV is a 75,497,472-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8640E18/32/36T-xxxV operates on a 1.8 V or 2.5 V

power supply. All inputs are 1.8 V or 2.5 V compatible.

Separate output power (V

) pins are used to decouple

DDQ

output noise from the internal circuits and are 1.8 V or 2.5 V

compatible.

Parameter Synopsis

-250

3.0

4.0

-200

3.0

5.0

-167

3.5

6.0

Unit

t_KQ

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

340

410

290

350

260

305

t_KQ

tCycle

6.5

7.5

8.0

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

245

280

220

250

210

240

Rev: 1.01 6/2006

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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与GS8640E18GT-167V相关器件

型号	品牌	获取价格	描述	数据表
GS8640E18GT-167VT	GSI	获取价格	Cache SRAM, 4MX18, 8ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8640E18GT-200	GSI	获取价格	100 TQFP
GS8640E18GT-200I	GSI	获取价格	100 TQFP
GS8640E18GT-200IV	GSI	获取价格	4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
GS8640E18GT-200T	GSI	获取价格	Cache SRAM, 4MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8640E18GT-200V	GSI	获取价格	4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
GS8640E18GT-200VT	GSI	获取价格	Cache SRAM, 4MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8640E18GT-250	GSI	获取价格	100 TQFP
GS8640E18GT-250I	GSI	获取价格	100 TQFP
GS8640E18GT-250IT	GSI	获取价格	Cache SRAM, 4MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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