Datasheet > GS832236C-225T

GS832236C-225T

更新时间： 2024-09-16 15:43:51

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
44页	1152K
描述
Cache SRAM, 1MX36, 6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

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GS832236C-225T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	209
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.69
最长访问时间：	6 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：	R-PBGA-B209	长度：	22 mm
内存密度：	37748736 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	209	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS832236C-225T 数据手册

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

250 MHz–133MHz

119- and 209-Pin BGA

Commercial Temp

2M x 18, 1M x 36, 512K x 72

2.5 V or 3.3 V V

Industrial Temp 36Mb S/DCD Sync Burst SRAMs

2.5 V or 3.3 V I/O

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• On-chip parity encoding and error detection

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

SCD and DCD Pipelined Reads

The GS832218/36/72 is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

t_KQ

tCycle

2.3 2.5 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.6 7.5 ns

Curr (x18) 365 335 305 265 245 215 mA

Curr (x36) 560 510 460 400 370 330 mA

Curr (x72) 660 600 540 460 430 380 mA

3.3 V

2.5 V

Curr (x18) 360 330 305 260 240 215 mA

Curr (x36) 550 500 460 390 360 330 mA

Curr (x72) 640 590 530 450 420 370 mA

Flow

Through

2-1-1-1

Byte Write and Global Write

t_KQ

tCycle

6.0 6.5 7.5 8.5 10 11 ns

7.0 7.5 8.5 10 10 15 ns

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Curr (x18) 235 230 210 200 195 150 mA

Curr (x36) 300 300 270 270 270 200 mA

Curr (x72) 350 350 300 300 300 220 mA

3.3 V

2.5 V

FLXDrive™

Curr (x18) 235 230 210 200 195 145 mA

Curr (x36) 300 300 270 270 270 190 mA

Curr (x72) 340 340 300 300 300 220 mA

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Functional Description

Applications

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

The GS832218/36/72 is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Core and Interface Voltages

The GS832218/36/72 operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output power

(V_DDQ) pins are used to decouple output noise from the internal

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

circuits and are 3.3 V and 2.5 V compatible.

Rev: 1.00 10/2001

1/44

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

12 3 4 5 6 7...44

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与GS832236C-225T相关器件

型号	品牌	获取价格	描述	数据表
GS832236C-250T	GSI	获取价格	Cache SRAM, 1MX36, 6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832236E	ETC	获取价格	2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832236E-133	ETC	获取价格	2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832236E-133I	ETC	获取价格	2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832236E-133IT	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
GS832236E-133T	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
GS832236E-150	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
GS832236E-150I	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
GS832236E-150IV	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS832236E-150IVT	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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