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GS8162Z18B-133 PDF预览

GS8162Z18B-133

更新时间: 2024-11-05 03:05:11
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GSI 静态存储器
页数 文件大小 规格书
38页 1200K
描述
18Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8162Z18B-133 数据手册

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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)  
250 MHz133 MHz 2.5  
119, 165, & 209 BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2M, 4M, and 8M devices  
• Byte write operation (9-bit Bytes)  
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by  
the user to operate in Pipeline or Flow Through mode.  
Operating as a pipelined synchronous device, in addition to the  
rising-edge-triggered registers that capture input signals, the  
device incorporates a rising edge triggered output register. For  
read cycles, pipelined SRAM output data is temporarily stored  
by the edge-triggered output register during the access cycle  
and then released to the output drivers at the next rising edge of  
clock.  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119-, 165-, or 209-Bump BGA package  
Functional Description  
The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit  
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,  
NtRAM, NoBL or other pipelined read/double late write or  
flow through read/single late write SRAMs, allow utilization  
of all available bus bandwidth by eliminating the need to insert  
deselect cycles when the device is switched from read to write  
cycles.  
The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with  
GSI's high performance CMOS technology and is available in  
a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &  
x36), or 209-bump (x72) BGA package.  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
Pipeline  
3-1-1-1  
tKQ  
2.5  
4.0  
2.7  
4.4  
3.0  
5.0  
3.4  
6.0  
3.8  
6.7  
4.0  
7.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x36)  
Curr (x72)  
280  
330  
n/a  
255  
300  
n/a  
230  
270  
350  
200  
230  
300  
185 165  
215 190  
270 245  
mA  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18)  
Curr (x36)  
Curr (x72)  
275  
320  
n/a  
250  
295  
n/a  
230  
265  
335  
195  
225  
290  
180 165  
210 185  
260 235  
mA  
mA  
mA  
Flow  
Through  
2-1-1-1  
tKQ  
5.5  
5.5  
6.0  
6.0  
6.5  
6.5  
7.0  
7.0  
7.5  
7.5  
8.5  
8.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x36)  
Curr (x72)  
175  
200  
n/a  
165  
190  
n/a  
160  
180  
225  
150  
170  
115  
145 135  
165 150  
210 185  
mA  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18)  
Curr (x36)  
Curr (x72)  
175  
200  
n/a  
165  
190  
n/a  
160  
180  
225  
150  
170  
115  
145 135  
165 150  
210 185  
mA  
mA  
mA  
Rev: 2.21 11/2004  
1/38  
© 1999, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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