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GS8160F36T-8I PDF预览

GS8160F36T-8I

更新时间: 2024-11-10 10:46:59
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
23页 457K
描述
Standard SRAM, 512KX36, 8ns, CMOS, PQFP100

GS8160F36T-8I 数据手册

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Preliminary  
GS8160F18/32/36T-7/8/8.5/10/11  
7 ns–11 ns  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
1M x 18, 512K x 32, 512K x 36  
16Mb Sync Burst SRAMs  
2.5 V V  
DD  
2.5 V or 3.3 V I/O  
should be designed with VSS connected to the FT pin location  
Features  
to ensure the broadest access to multiple vendor sources.  
Boards designed with FT pin pads tied low may be stuffed with  
GSI’s pipeline/flow through-configurable Burst RAMs or any  
vendor’s flow through or configurable Burst SRAM. Boards  
designed with the FT pin location tied high or floating must  
employ a non-configurable flow through Burst RAM, like this  
RAM, to achieve flow through functionality.  
• Flow Through mode operation; Pin 14 = No Connect  
• 2.5 V +10%/–5% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
-7 -7.5 -8 -8.5 -10 -11 Unit  
Flow  
tKQ  
tCycle  
7.0 7.5  
8
8.5 10 11 ns  
Through  
2-1-1-1  
8.5 10 10 10 10 15 ns  
205 185 185 185 185 140 mA  
240 210 210 210 210 160 mA  
240 210 210 210 210 160 mA  
Sleep Mode  
Curr (x18)  
Curr (x32)  
Curr (x36)  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
Functional Description  
The GS8160F18/32/36T operates on a 2.5 V power supply. All  
input are 3.3 V- and 2.5 V-compatible. Separate output power  
(VDDQ) pins are used to decouple output noise from the  
Applications  
The GS8160F18/32/36T is a 18,874,368-bit (16,777,216-bit  
for x32 version) high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
internal circuits and are 3.3 V- and 2.5 V-compatible.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Designing For Compatibility  
The JEDEC standard for Burst RAMS calls for a FT mode pin  
option on Pin 14. Board sites for flow through Burst RAMS  
Rev: 2.06 11/2000  
1/23  
© 1999, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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