Preliminary
GS8160V18/32/36AT-350/333/300/250/200/150
350 MHz–150 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18, 512K x 32, 512K x 36
1.8 V VDD
1.8 V I/O
18Mb Sync Burst SRAMs
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
Byte Write and Global Write
Functional Description
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Applications
The GS8160V18/32/36AT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160V18/32/36AT operates on a 1.8 V power supply.
All input are 1.8 V compatible. Separate output power (V
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
)
DDQ
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Parameter Synopsis
-350 -333 -300 -250 -200 -150 Unit
tKQ
1.8
2.85
2.0
3.0
2.2
3.3
2.3
4.0
2.7
5.0
3.3
6.7
ns
ns
tCycle
Pipeline
3-1-1-1
395
455
370
430
335
390
280
330
230
270
185
210
mA
mA
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
4.5
4.5
4.7
4.7
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Flow
Through
2-1-1-1
270
305
250
285
230
270
210
240
185
205
170
190
mA
mA
Curr (x18)
Curr (x32/x36)
Rev: 1.00a 6/2003
1/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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