GS8160FZ18/36DGT-6.5
6.5 ns
100-Pin TQFP
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAMs
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Features
Functional Description
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• Flow Through mode operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and
144Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
The GS8160FZ18/36DGT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• RoHS-compliant 100-lead TQFP package available
Parameter Synopsis
-6.5
Unit
t
6.5
6.5
ns
ns
KQ
Flow Through
2-1-1-1
tCycle
Curr (x18)
Curr (x36)
205
225
mA
mA
Rev: 1.00 10/2013
1/20
© 2013, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.