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GS8160F36T-7.5I PDF预览

GS8160F36T-7.5I

更新时间: 2024-01-03 07:46:23
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
22页 546K
描述
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GS8160F36T-7.5I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP, QFP100,.63X.87
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.65最长访问时间:7.5 ns
其他特性:FLOW-THROUGH ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:18874368 bit内存集成电路类型:CACHE SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5,2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
最小待机电流:2.38 V子类别:SRAMs
最大压摆率:0.177 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

GS8160F36T-7.5I 数据手册

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GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5  
Mode Pin Functions  
Mode Name  
Pin Name  
State  
Function  
Linear Burst  
Interleaved Burst  
Active  
L
Burst Order Control  
LBO  
H
L or NC  
H
Power Down Control  
ZZ  
Standby, I = I  
DD SB  
Note:  
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in  
the above tables.  
Burst Counter Sequences  
Linear Burst Sequence  
A[1:0] A[1:0] A[1:0] A[1:0]  
Interleaved Burst Sequence  
A[1:0] A[1:0] A[1:0] A[1:0]  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Note:  
Note:  
The burst counter wraps to initial state on the 5th clock.  
The burst counter wraps to initial state on the 5th clock.  
BPR 1999.05.18  
Byte Write Truth Table  
Function  
Read  
GW  
H
BW  
H
L
BA  
X
BB  
X
BC  
X
BD  
X
Notes  
1
Read  
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a  
Write byte b  
Write byte c  
Write byte d  
Write all bytes  
Write all bytes  
H
L
2, 3  
H
L
H
H
H
L
2, 3  
H
L
H
H
L
2, 3, 4  
2, 3, 4  
2, 3, 4  
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:  
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.  
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.  
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.  
4. Bytes C” and “D” are only available on the x32 and x36 versions.  
Rev: 2.12 11/2004  
7/22  
© 1999, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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