GS72116AJ-8IT

更新时间： 2024-11-23 13:07:59

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
18页	491K
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中文翻译

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数据手册

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GS72116AJ-8IT 数据手册

GS72116ATP/J/T/U

SOJ, TSOP, FP-BGA, TQFP

Commercial Temp

7, 8, 10, 12 ns

3.3 V V_DD

128K x 16

Industrial Temp

2Mb Asynchronous SRAM

Center V_DDand V_SS

Features

SOJ 128K x 16-Pin Configuration

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 145/125/100/85 mA at

minimum cycle time

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

Top view

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

DQ1

DQ2

DQ3

DQ4

V_DD

DQ16

DQ15

DQ14

J: 400 mil, 44-pin SOJ package

TP: 400 mil, 44-pin TSOP Type II package

T: 10 mm x 10 mm, 44-pin TQFP

U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

DQ13

V_SS

V_DD

DQ12

DQ11

DQ10

DQ9

44-pin

SOJ

V_SS

DQ5

DQ6

DQ7

DQ8

Description

The GS72116A is a high speed CMOS Static RAM organized

as 131,072 words by 16 bits. Static design eliminates the need

for external clocks or timing strobes. The GS operates on a sin-

gle 3.3 V power supply and all inputs and outputs are TTL-

compatible. The GS72116A is available in a 6 mm x 8 mm

Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as

well as in 400 mil SOJ and 400 mil TSOP Type-II packages.

A15

A14

A13

A12

A16

A10

A11

Package J

Pin Descriptions

Symbol

A0–A16

Description

Address input

DQ¹–DQ¹⁶

Data input/output

Chip enable input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Write enable input

Output enable input

+3.3 V power supply

Ground

No connect

Rev: 1.04a 10/2002

1/18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...18

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GS72116AT-12T	GSI	获取价格	暂无描述