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GS72116ATP-10 PDF预览

GS72116ATP-10

更新时间: 2024-11-26 07:02:07
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
18页 491K
描述
128K x 16 2Mb Asynchronous SRAM

GS72116ATP-10 数据手册

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GS72116ATP/J/T/U  
SOJ, TSOP, FP-BGA, TQFP  
Commercial Temp  
7, 8, 10, 12 ns  
3.3 V VDD  
128K x 16  
Industrial Temp  
2Mb Asynchronous SRAM  
Center VDD and VSS  
Features  
SOJ 128K x 16-Pin Configuration  
• Fast access time: 7, 8, 10, 12 ns  
• CMOS low power operation: 145/125/100/85 mA at  
minimum cycle time  
A4  
A3  
A5  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
1
A6  
2
• Single 3.3 V power supply  
A2  
A7  
3
• All inputs and outputs are TTL-compatible  
• Byte control  
A1  
OE  
4
Top view  
A0  
UB  
5
• Fully static operation  
CE  
LB  
6
• Industrial Temperature Option: 40° to 85°C  
• Package line up  
DQ1  
DQ2  
DQ3  
DQ4  
VDD  
DQ16  
DQ15  
DQ14  
7
8
J: 400 mil, 44-pin SOJ package  
TP: 400 mil, 44-pin TSOP Type II package  
T: 10 mm x 10 mm, 44-pin TQFP  
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package  
9
10  
11  
12  
13  
14  
15  
DQ13  
VSS  
VDD  
DQ12  
DQ11  
DQ10  
DQ9  
NC  
44-pin  
SOJ  
VSS  
DQ5  
DQ6  
DQ7  
DQ8  
WE  
Description  
16  
17  
18  
The GS72116A is a high speed CMOS Static RAM organized  
as 131,072 words by 16 bits. Static design eliminates the need  
for external clocks or timing strobes. The GS operates on a sin-  
gle 3.3 V power supply and all inputs and outputs are TTL-  
compatible. The GS72116A is available in a 6 mm x 8 mm  
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as  
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.  
A15  
A14  
A13  
A12  
A16  
A8  
A9  
19  
20  
21  
22  
A10  
A11  
NC  
Package J  
Pin Descriptions  
Symbol  
A0A16  
Description  
Address input  
DQ1DQ16  
CE  
Data input/output  
Chip enable input  
Lower byte enable input  
(DQ1 to DQ8)  
LB  
Upper byte enable input  
(DQ9 to DQ16)  
UB  
WE  
OE  
Write enable input  
Output enable input  
+3.3 V power supply  
V
DD  
V
Ground  
SS  
NC  
No connect  
Rev: 1.04a 10/2002  
1/18  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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