Datasheet > GS72116AT-15IT

GS72116AT-15IT

更新时间： 2024-11-24 06:35:03

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
17页	261K
描述
SRAM

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中文翻译

获取价格

数据手册

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GS72116AT-15IT 数据手册

GS72116ATP/J/T/U

6, 8, 10, 12, 15 ns

SOJ, TSOP, FP-BGA, TQFP

Commercial Temp

128K x 16

3.3 V V

Industrial Temp

2Mb Asynchronous SRAM

Center V and V

Features

SOJ 128K x 16-Pin Configuration

• Fast access time: 6, 8, 10, 12, 15 ns

• CMOS low power operation: 165/125/100/85/65 mA at

minimum cycle time

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

Top view

DQ1

DQ2

DQ3

DQ4

DQ16

DQ15

DQ14

J: 400 mil, 44-pin SOJ package

TP: 400 mil, 44-pin TSOP Type II package

T: 10 mm x 10 mm, 44-pin TQFP

U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

DQ13

44-pin

SOJ

DQ5

DQ6

DQ7

DQ8

DQ12

DQ11

DQ10

DQ9

Description

The GS72116A is a high speed CMOS Static RAM organized

as 131,072 words by 16 bits. Static design eliminates the need

for external clocks or timing strobes. The GS operates on a sin-

gle 3.3 V power supply and all inputs and outputs are TTL-

compatible. The GS72116A is available in a 6 mm x 8 mm

Fine Pitch BGA package,, a 10 mm x 10 mm TQFP package,

as well as in 400 mil SOJ and 400 mil TSOP Type-II packages.

A15

A14

A13

A12

A10

A11

A16

Package J

Pin Descriptions

Symbol

A0–A16

Description

Address input

DQ1–DQ16

Data input/output

Chip enable input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Write enable input

Output enable input

+3.3 V power supply

V_DD

V_SS

Ground

No connect

Rev: 1.02 10/2001

1/17

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...17

中文翻译

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