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GM76C8128CLLW-70 PDF预览

GM76C8128CLLW-70

更新时间: 2022-01-19 09:18:00
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
13页 111K
描述
x8 SRAM

GM76C8128CLLW-70 数据手册

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GM76C8128CL/CLL-W  
LG Semicon Co.,Ltd.  
131,072 WORDS x 8 BIT  
CMOS STATIC RAM  
Description  
Pin Configuration  
The GM76C8128CL/CLL-W is a 1,048,576 bits  
static random access memory organized as 131,072  
words by 8 bits. Using a 0.6um advanced CMOS  
technology and operated from a single 2.7V to 5.5V  
supply. Advanced circuit technique provide both high  
speed and low power consumption. The device is  
placed in a low power standby mode with /CS1 high  
or CS2 low and the output enable (/OE) allows fast  
memory access. Thus it is suitable for high speed and  
low power applications, especially where battery  
back-up is required.  
NC  
A16  
A14  
1
32 VCC  
2
3
4
5
6
31  
A15  
30 CS2  
29 /WE  
A12  
A7  
28  
A13  
A6  
27 A8  
26 A9  
25 A11  
A5  
A4  
A3  
A2  
A1  
A0  
7
8
9
24  
/OE  
Features  
10  
11  
23  
A10  
* Fast Speed : 55/70ns at Vcc=5V+/ - 10%  
120/150ns at Vcc=3V+/ - 10%  
22  
/CS1  
12  
21  
I/O7  
* Low Power Standby and Low Power Operation  
-Standby : 0.11mW Max. at Vcc=5V+/ - 10%  
49.5uW Max. at Vcc=3V+/ - 10%  
-Operation : 385mW Max. at Vcc=5V+/ - 10%  
66mW Max. at Vcc=3V+/ - 10%  
I/O0 13  
I/O1 14  
20 I/O6  
19 I/O5  
15  
18  
I/O2  
I/O4  
16  
17  
VSS  
I/O3  
* Completely Static RAM : No Clock or Timing  
Strobe Required  
* Equal Access and Cycle Time  
* TTL compatible inputs and outputs  
* Capability of Battery Back-up Operation  
* Single +2.7V ~ +5.5V Operation  
* Standard 32 DIP, SOP and TSOP I  
(Top View)  
Block Diagram  
A0  
A1  
A2  
MEMORY CELL ARRAY  
1024 x 128 x 8  
10  
1024  
X
Decoder  
(128K x 8)  
Address  
Buffer  
Pin Description  
Pin  
A0-A16  
/WE  
Function  
Address Inputs  
A14  
A15  
A16  
128 x 8  
7
128  
Y
Column Select  
Decorder  
Write Enable Input  
Chip Select Input  
Output Enable Input  
Data Inputs/Outputs  
Power Supply (2.7V~5.5V)  
Ground  
/CS1, CS2  
/OE  
/CS1, CS2  
8
/CS1  
CS2  
Chip  
Control  
I/O0-I/O7  
VCC  
/OE, /WE  
/OE  
I/O Buffer  
Chip  
Control  
/WE  
VSS  
NC  
No Connection  
121  

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