Datasheet > GM76C8128CLLWT-70

GM76C8128CLLWT-70

更新时间： 2024-11-09 23:53:51

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
13页	111K
描述
x8 SRAM

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GM76C8128CL/CLL-W

LG Semicon Co.,Ltd.

131,072 WORDS x 8 BIT

CMOS STATIC RAM

Description

Pin Configuration

The GM76C8128CL/CLL-W is a 1,048,576 bits

static random access memory organized as 131,072

words by 8 bits. Using a 0.6um advanced CMOS

technology and operated from a single 2.7V to 5.5V

supply. Advanced circuit technique provide both high

speed and low power consumption. The device is

placed in a low power standby mode with /CS1 high

or CS2 low and the output enable (/OE) allows fast

memory access. Thus it is suitable for high speed and

low power applications, especially where battery

back-up is required.

A16

A14

32 VCC

A15

30 CS2

29 /WE

A12

A13

27 A8

26 A9

25 A11

/OE

Features

A10

* Fast Speed : 55/70ns at Vcc=5V+/ - 10%

120/150ns at Vcc=3V+/ - 10%

/CS1

I/O7

* Low Power Standby and Low Power Operation

-Standby : 0.11mW Max. at Vcc=5V+/ - 10%

49.5uW Max. at Vcc=3V+/ - 10%

-Operation : 385mW Max. at Vcc=5V+/ - 10%

66mW Max. at Vcc=3V+/ - 10%

I/O0 13

I/O1 14

20 I/O6

19 I/O5

I/O2

I/O4

VSS

I/O3

* Completely Static RAM : No Clock or Timing

Strobe Required

* Equal Access and Cycle Time

* TTL compatible inputs and outputs

* Capability of Battery Back-up Operation

* Single +2.7V ~ +5.5V Operation

* Standard 32 DIP, SOP and TSOP I

(Top View)

Block Diagram

MEMORY CELL ARRAY

1024 x 128 x 8

1024

Decoder

(128K x 8)

Address

Buffer

Pin Description

A0-A16

/WE

Function

Address Inputs

A14

A15

A16

128 x 8

128

Column Select

Decorder

Write Enable Input

Chip Select Input

Output Enable Input

Data Inputs/Outputs

Power Supply (2.7V~5.5V)

Ground

/CS1, CS2

/OE

/CS1, CS2

/CS1

CS2

Chip

Control

I/O0-I/O7

VCC

/OE, /WE

/OE

I/O Buffer

Chip

Control

/WE

VSS

No Connection

121

12 3 4 5 6 7...13

中文翻译

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