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GAL26V12C-20LJI PDF预览

GAL26V12C-20LJI

更新时间: 2024-11-07 23:53:35
品牌 Logo 应用领域
其他 - ETC 可编程逻辑器件
页数 文件大小 规格书
16页 205K
描述
Electrically-Erasable PLD

GAL26V12C-20LJI 数据手册

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GAL26V12  
High Performance E2CMOS PLD  
Generic Array LogicTM  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 7.5 ns Maximum Propagation Delay  
— Fmax = 142.8 MHz  
I/CLK 1  
INPUT  
I/O/Q  
PRESET  
— 4.5 ns Maximum from Clock Input to Data Output  
— TTL Compatible 16 mA Outputs  
8
OLMC 0  
INPUT  
— UltraMOS® Advanced CMOS Technology  
8
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
OLMC 1  
OLMC 2  
• LOW POWER CMOS  
— 90 mA Typical Icc  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/Guaranteed 100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
INPUT  
INPUT/CLK 2  
INPUT  
10  
12  
14  
16  
16  
14  
12  
10  
8
OLMC 3  
OLMC 4  
OLMC 5  
INPUT  
• TWELVE OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
INPUT  
OLMC 6  
OLMC 7  
OLMC 8  
OLMC 9  
OLMC 10  
OLMC 11  
• PRELOAD AND POWER-ON RESET OF REGISTERS  
— 100% Functional Testability  
INPUT  
INPUT  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
INPUT  
INPUT  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
INPUT  
DESCRIPTION  
8
INPUT  
The GAL26V12, at 7.5ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest perform-  
ance available of any 26V12 device on the market. E2 technol-  
ogy offers high speed (<100ms) erase times, providing the ability  
to reprogram or reconfigure the device quickly and efficiently.  
RESET  
PACKAGE DIAGRAMS  
DIP  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. The GAL26V12 is fully function/fuse map/parametric  
compatible with other 26V12 devices.  
1
28  
I
I/CLK1  
PLCC  
I/O/Q  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
GND  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
Unique test circuitry and reprogrammable cells allow complete  
AC, DC, and functional testing during manufacture. As a result,  
LATTICE is able to guarantee 100% field programmability and  
functionality of all GAL® products. LATTICE also guarantees 100  
erase/rewrite cycles.  
I/CLK2  
GAL  
26V12  
I
4
2
28  
26  
25  
I
5
7
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
GND  
I/O/Q  
I/O/Q  
Vcc  
7
I
I
I
I
I
21  
VCC  
23  
GAL26V12  
Top View  
I
I
I
I
9
21  
19  
11  
I
I
12  
14  
16  
18  
14  
15 I/O/Q  
I
Copyright ©2000 Lattice Semiconductor Corp. GAL, E2CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-  
tor Corp. The specifications herein are subject to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.  
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556  
November 2000  

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