Datasheet > GAL26V12C-7LJ

GAL26V12C-7LJ

更新时间： 2024-09-20 23:53:35

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件
页数	文件大小	规格书
16页	205K
描述
Electrically-Erasable PLD

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GAL26V12C-7LJ 数据手册

GAL26V12

High Performance E²CMOS PLD

Generic Array Logic^TM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 142.8 MHz

I/CLK 1

INPUT

I/O/Q

PRESET

— 4.5 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

OLMC 0

INPUT

— UltraMOS^®Advanced CMOS Technology

I/O/Q

OLMC 1

OLMC 2

• LOW POWER CMOS

— 90 mA Typical Icc

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/Guaranteed 100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

INPUT

INPUT/CLK 2

INPUT

OLMC 3

OLMC 4

OLMC 5

INPUT

• TWELVE OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

INPUT

OLMC 6

OLMC 7

OLMC 8

OLMC 9

OLMC 10

OLMC 11

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability

INPUT

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

INPUT

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

INPUT

DESCRIPTION

INPUT

The GAL26V12, at 7.5ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E²) floating gate technology to provide the highest perform-

ance available of any 26V12 device on the market. E²technol-

ogy offers high speed (<100ms) erase times, providing the ability

to reprogram or reconfigure the device quickly and efficiently.

RESET

PACKAGE DIAGRAMS

DIP

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL26V12 is fully function/fuse map/parametric

compatible with other 26V12 devices.

I/CLK1

PLCC

I/O/Q

GND

I/O/Q

Unique test circuitry and reprogrammable cells allow complete

AC, DC, and functional testing during manufacture. As a result,

LATTICE is able to guarantee 100% field programmability and

functionality of all GAL^®products. LATTICE also guarantees 100

erase/rewrite cycles.

I/CLK2

GAL

26V12

I/O/Q

GND

I/O/Q

Vcc

VCC

GAL26V12

Top View

15 I/O/Q

tor Corp. The specifications herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.

Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556

November 2000

12 3 4 5 6 7...16

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