Datasheet > GAL20LV8ZD

GAL20LV8ZD

更新时间： 2024-11-07 22:51:03

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
18页	284K
描述
Low Voltage, Zero Power E2CMOS PLD Generic Array Logic

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中文翻译

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数据手册

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GAL20LV8ZD 数据手册

GAL20LV8ZD

Low Voltage, Zero Power E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

I/CLK

• 3.3V LOW VOLTAGE, ZERO POWER OPERATION

— JEDEC Compatible 3.3V Interface Standard

— Interfaces with Standard 5V TTL Devices

— 50µA Typical Standby Current (100µA Max.)

— 45mA Typical Active Current (55mA Max.)

— Dedicated Power-down Pin

• HIGH PERFORMANCE E²CMOS TECHNOLOGY

— TTL Compatible Balanced 8 mA Output Drive

— 15 ns Maximum Propagation Delay

IMUX

CLK

I/O/Q

OLMC

I/O/Q

DPP

— Fmax = 62.5 MHz

— 10 ns Maximum from Clock Input to Data Output

— UltraMOS^®Advanced CMOS Technology

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— Glue Logic for 3.3V Systems

— Ideal for Mixed 3.3V and 5V Systems

OLMC

IMUX

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/OE

Description

Pin Configuration

The GAL20LV8ZD, at 100 µAstandby current and 15ns propagation

delay provides the highest speed low-voltage PLD available in the

market. The GAL20LV8ZD is manufactured using Lattice

Semiconductor's advanced 3.3V E²CMOS process, which com-

bines CMOS with Electrically Erasable (E²) floating gate technology.

PLCC

DPP

25 I/O/Q

The GAL20LV8ZD utilizes a dedicated power-down pin (DPP) to

put the device into standby mode. It has 19 inputs available to the

AND array and is capable of interfacing with both 3.3V and stan-

dard 5V devices.

I/O/Q

GAL20LV8ZD

Top View

I/O/Q

21 I/O/Q

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write cycles

and data retention in excess of 20 years are specified.

I/O/Q

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 1997

20lv8zd_03

12 3 4 5 6 7...18

中文翻译

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与GAL20LV8ZD相关器件

型号	品牌	获取价格	描述	数据表
GAL20LV8ZD-15QJ	LATTICE	获取价格	Low Voltage, Zero Power E2CMOS PLD Generic Array Logic
GAL20LV8ZD-25QJ	LATTICE	获取价格	Low Voltage, Zero Power E2CMOS PLD Generic Array Logic
GAL20RA10	LATTICE	获取价格	High-Speed Asynchronous E2CMOS PLD Generic Ar
GAL20RA10-12LJ	LATTICE	获取价格	EE PLD, 12ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
GAL20RA10-12LP	ETC	获取价格	Electrically-Erasable PLD
GAL20RA10-15D	ETC	获取价格	ASIC
GAL20RA10-15J	ETC	获取价格	ASIC
GAL20RA10-15JC	TI	获取价格	EE PLD, 15ns, CDIP24, CERAMIC, DIP-24
GAL20RA10-15JC	NSC	获取价格	IC EE PLD, 15 ns, CDIP24, CERAMIC, DIP-24, Programmable Logic Device
GAL20RA10-15LJ	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

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