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GAL20LV8ZD-15QJ PDF预览

GAL20LV8ZD-15QJ

更新时间： 2024-09-19 22:25:15
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
18页 284K
描述
Low Voltage, Zero Power E2CMOS PLD Generic Array Logic

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GAL20LV8ZD-15QJ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-28
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.83Is Samacsys：N
其他特性：REGISTER PRELOAD; POWER-UP RESET架构：PAL-TYPE
最大时钟频率：45.5 MHzJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.5062 mm
湿度敏感等级：1专用输入次数：11
I/O 线路数量：8输入次数：19
输出次数：8产品条款数：64
端子数量：28最高工作温度：75 °C
最低工作温度：组织：11 DEDICATED INPUTS, 8 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225电源：3.3 V
可编程逻辑类型：EE PLD传播延迟：18 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn85Pb15)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.5062 mmBase Number Matches：1

GAL20LV8ZD-15QJ 数据手册

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GAL20LV8ZD  
Low Voltage, Zero Power E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
I/CLK  
• 3.3V LOW VOLTAGE, ZERO POWER OPERATION  
— JEDEC Compatible 3.3V Interface Standard  
— Interfaces with Standard 5V TTL Devices  
— 50µA Typical Standby Current (100µA Max.)  
— 45mA Typical Active Current (55mA Max.)  
— Dedicated Power-down Pin  
• HIGH PERFORMANCE E2CMOS TECHNOLOGY  
— TTL Compatible Balanced 8 mA Output Drive  
— 15 ns Maximum Propagation Delay  
I
IMUX  
I
CLK  
I/O/Q  
8
8
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
DPP  
— Fmax = 62.5 MHz  
— 10 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
8
8
8
I
I
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
I
I
8
8
8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— Glue Logic for 3.3V Systems  
I
— Ideal for Mixed 3.3V and 5V Systems  
OLMC  
IMUX  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
I
I
OE  
I
I/OE  
Description  
Pin Configuration  
The GAL20LV8ZD, at 100 µAstandby current and 15ns propagation  
delay provides the highest speed low-voltage PLD available in the  
market. The GAL20LV8ZD is manufactured using Lattice  
Semiconductor's advanced 3.3V E2CMOS process, which com-  
bines CMOS with Electrically Erasable (E2) floating gate technology.  
PLCC  
4
2
28  
26  
5
7
DPP  
25 I/O/Q  
The GAL20LV8ZD utilizes a dedicated power-down pin (DPP) to  
put the device into standby mode. It has 19 inputs available to the  
AND array and is capable of interfacing with both 3.3V and stan-  
dard 5V devices.  
I
I
I/O/Q  
GAL20LV8ZD  
Top View  
23  
I/O/Q  
NC  
NC  
I
I
I
9
21 I/O/Q  
I/O/Q  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result,  
Lattice Semiconductor delivers 100% field programmability and  
functionality of all GAL products. In addition, 100 erase/write cycles  
and data retention in excess of 20 years are specified.  
11  
19  
18  
I/O/Q  
12  
14  
16  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
December 1997  
1
20lv8zd_03  
1234567...18

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