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GAL16V8C-7LP PDF预览

GAL16V8C-7LP

更新时间: 2024-10-27 22:51:03
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
23页 395K
描述
High Performance E2CMOS PLD Generic Array Logic

GAL16V8C-7LP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.52其他特性:REGISTER PRELOAD; POWER-UP RESET
架构:PAL-TYPE最大时钟频率:83.3 MHz
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.125 mm专用输入次数:8
I/O 线路数量:8输入次数:18
输出次数:8产品条款数:64
端子数量:20最高工作温度:75 °C
最低工作温度:组织:8 DEDICATED INPUTS, 8 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):225电源:5 V
可编程逻辑类型:EE PLD传播延迟:9 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.62 mmBase Number Matches:1

GAL16V8C-7LP 数据手册

 浏览型号GAL16V8C-7LP的Datasheet PDF文件第1页浏览型号GAL16V8C-7LP的Datasheet PDF文件第2页浏览型号GAL16V8C-7LP的Datasheet PDF文件第3页浏览型号GAL16V8C-7LP的Datasheet PDF文件第5页浏览型号GAL16V8C-7LP的Datasheet PDF文件第6页浏览型号GAL16V8C-7LP的Datasheet PDF文件第7页 
Specifications GAL16V8  
REGISTERED MODE  
In the Registered mode, macrocells are configured as dedicated  
registered outputs or as I/O functions.  
mode. Dedicated input or output functions can be implemented  
as subsets of the I/O function.  
Architecture configurations available in this mode are similar to  
the common 16R8 and 16RP4 devices with various permutations  
of polarity, I/O and register placement.  
Registered outputs have eight product terms per output. I/O's  
have seven product terms per output.  
The JEDEC fuse numbers, including the User Electronic Signature  
(UES) fuses and the Product Term Disable (PTD) fuses, are  
shown on the logic diagram on the following page.  
All registered macrocells share common clock and output enable  
control pins. Any macrocell can be configured as registered or  
I/O. Up to eight registers or up to eight I/O's are possible in this  
CLK  
Registered Configuration for Registered Mode  
- SYN=0.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=0 defines this output configuration.  
- Pin 1 controls common CLK for the registered outputs.  
- Pin 11 controls common OE for the registered outputs.  
- Pin 1 & Pin 11 are permanently configured as CLK &  
OE.  
D
Q
Q
XOR  
OE  
Combinatorial Configuration for Registered Mode  
- SYN=0.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1 defines this output configuration.  
- Pin 1 & Pin 11 are permanently configured as CLK &  
OE.  
XOR  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
1996 Data Book  
3-68  

GAL16V8C-7LP 替代型号

型号 品牌 替代类型 描述 数据表
GAL16V8D-7LPN LATTICE

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High Performance E2CMOS PLD Generic Array Log
GAL16V8D-7LP LATTICE

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GAL16V8D-7LPNI LATTICE

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High Performance E2CMOS PLD Generic Array Log

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