Datasheet > 可编程逻辑 > 可编程逻辑器件> GAL16V8C-7LP

GAL16V8C-7LP

更新时间： 2024-02-12 22:39:22

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
23页	395K
描述
High Performance E2CMOS PLD Generic Array Logic

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GAL16V8C-7LP 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	PLASTIC, DIP-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.55	其他特性：	REGISTER PRELOAD; POWER-UP RESET
架构：	PAL-TYPE	最大时钟频率：	83.3 MHz
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e0
长度：	26.125 mm	专用输入次数：	8
I/O 线路数量：	8	输入次数：	18
输出次数：	8	产品条款数：	64
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8 DEDICATED INPUTS, 8 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	9 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm	Base Number Matches：	1

GAL16V8C-7LP 数据手册

Specifications GAL16V8

OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic

macrocell. It should be noted that actual implementation is ac-

complished by development software/hardware and is completely

transparent to the user.

PAL Architectures

Emulated by GAL16V8

GAL16V8

Global OLMC Mode

16R8

16R6

16R4

16RP8

16RP6

16RP4

Registered

There are three global OLMC configuration modes possible:

simple, complex, and registered. Details of each of these

modes are illustrated in the following pages. Two global bits, SYN

and AC0, control the mode configuration for all macrocells. The

XOR bit of each macrocell controls the polarity of the output in any

of the three modes, while the AC1 bit of each of the macrocells

controls the input/output configuration. These two global and 16

individual architecture bits define all possible configurations in a

GAL16V8 . The information given on these architecture bits is

only to give a better understanding of the device. Compiler soft-

ware will transparently set these architecture bits from the pin

definitions, so the user should not need to directly manipulate

these architecture bits.

16L8

16H8

16P8

Complex

10L8

12L6

14L4

16L2

10H8

12H6

14H4

16H2

10P8

12P6

14P4

16P2

Simple

The following is a list of the PAL architectures that the GAL16V8

can emulate. It also shows the OLMC mode under which the

GAL16V8 emulates the PAL architecture.

COMPILER SUPPORT FOR OLMC

Software compilers support the three different global OLMC

modes as different device types. These device types are listed

in the table below. Most compilers have the ability to automati-

cally select the device type, generally based on the register usage

and output enable (OE) usage. Register usage on the device

forces the software to choose the registered mode. All combina-

torial outputs with OE controlled by the product term will force the

software to choose the complex mode. The software will choose

the simple mode only when all outputs are dedicated combinatorial

without OE control. The different device types listed in the table

can be used to override the automatic device selection by the

software. For further details, refer to the compiler software

manuals.

In registered mode pin 1 and pin 11 are permanently configured

as clock and output enable, respectively. These pins cannot be

configured as dedicated inputs in the registered mode.

In complex mode pin 1 and pin 11 become dedicated inputs and

use the feedback paths of pin 19 and pin 12 respectively. Because

of this feedback path usage, pin 19 and pin 12 do not have the

feedback option in this mode.

In simple mode all feedback paths of the output pins are routed

via the adjacent pins. In doing so, the two inner most pins ( pins

15 and 16) will not have the feedback option as these pins are

always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user

must pay special attention to the following restrictions in each

mode.

Registered

Complex

Simple

Auto Mode Select

ABEL

CUPL

LOG/iC

OrCAD-PLD

PLDesigner

TANGO-PLD

P16V8R

G16V8MS

GAL16V8_R

"Registered"¹

P16V8R²

P16V8C

G16V8MA

GAL16V8_C7

"Complex"¹

P16V8C²

P16V8AS

G16V8AS

GAL16V8_C8

"Simple"¹

P16V8

G16V8

GAL16V8

GAL16V8A

P16V8A

G16V8

P16V8C²

G16V8R

G16V8C

G16V8AS³

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later.

1996 Data Book

3-67

1 234 5 6 7...23

中文翻译

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GAL16V8C-7LP 替代型号

型号	品牌	替代类型	描述	数据表
GAL16V8D-7LPNI	LATTICE	功能相似	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-7LPN	LATTICE	完全替代	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-7LP	LATTICE	类似代替	High Performance E2CMOS PLD Generic Array Logic

与GAL16V8C-7LP相关器件

型号	品牌	获取价格	描述	数据表
GAL16V8C-7LPI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8C-7LR/883	LATTICE	获取价格	EE PLD, 9ns, PAL-Type, CMOS, CQCC20, LCC-20
GAL16V8D	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-10LD	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-10LD/833	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-10LD/883	ETC	获取价格	Electrically-Erasable PLD
GAL16V8D-10LJ	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-10LJI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-10LJN	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-10LJNI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log

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