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GAL16V8D-10LPN PDF预览

GAL16V8D-10LPN

更新时间： 2024-01-12 13:29:01
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
24页 650K
描述
High Performance E2CMOS PLD Generic Array Logic⑩

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GAL16V8D-10LPN 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：PLASTIC, DIP-20针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.19
Is Samacsys：N架构：PAL-TYPE
最大时钟频率：66.7 MHzJESD-30 代码：R-PDIP-T20
JESD-609代码：e0长度：26.162 mm
专用输入次数：8I/O 线路数量：8
输入次数：18输出次数：8
产品条款数：64端子数量：20
最高工作温度：70 °C最低工作温度：
组织：8 DEDICATED INPUTS, 8 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：EE PLD
传播延迟：10 ns认证状态：Not Qualified
座面最大高度：5.334 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.62 mm
Base Number Matches：1

GAL16V8D-10LPN 数据手册

 浏览型号GAL16V8D-10LPN的Datasheet PDF文件第2页浏览型号GAL16V8D-10LPN的Datasheet PDF文件第3页浏览型号GAL16V8D-10LPN的Datasheet PDF文件第4页浏览型号GAL16V8D-10LPN的Datasheet PDF文件第5页浏览型号GAL16V8D-10LPN的Datasheet PDF文件第6页浏览型号GAL16V8D-10LPN的Datasheet PDF文件第7页 
GAL16V8  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
I/CLK  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 3.5 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
CLK  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
8
8
OLMC  
— 3.0 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
I
I
I
I
I
I
I
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typ Icc on Low Power Device  
— 45mA Typ Icc on Quarter Power Device  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
8
8
8
8
8
8
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
— Also Emulates 20-pin PAL® Devices with Full  
Function/Fuse Map/Parametric Compatibility  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I/O/Q  
I/OE  
OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
• LEAD-FREE PACKAGE OPTIONS  
Pin Configuration  
PLCC  
Description  
I
I
I/CLK Vcc I/O/Q  
2
20  
DIP  
18  
16  
I/O/Q  
4
6
I
The GAL16V8, at 3.5 ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest speed  
performance available in the PLD market. High speed erase times  
(<100ms) allow the devices to be reprogrammed quickly and ef-  
ficiently.  
I/O/Q  
I/O/Q  
I
1
20  
Vcc  
I/CLK  
GAL16V8  
Top View  
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/OE  
I
I/O/Q  
I/O/Q  
I
I
I
GAL  
14  
I
8
9
I
11  
13  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configura-  
tions possible with the GAL16V8 are the PAL architectures listed  
in the table of the macrocell description section. GAL16V8 devices  
are capable of emulating any of these PAL architectures with full  
function/fuse map/parametric compatibility.  
16V8  
GND I/OE I/O/Q I/O/Q  
5
I
I
SOIC  
15  
I/CLK  
I
1
20  
Vcc  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/OE  
I
I
GAL  
16V8  
Top  
5
I
I
I
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
15  
11  
10  
11  
GND  
I
I
View  
I
10  
GND  
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
1
16v8_11  
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