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FQV243L10PFI PDF预览

FQV243L10PFI

更新时间: 2024-02-17 08:42:49
品牌 Logo 应用领域
联笙电子 - AMICC 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
43页 394K
描述
FIFO, 2KX18, 6.5ns, Synchronous, CMOS, PQFP80

FQV243L10PFI 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:QFP, QFP80,.64SQReach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.89最长访问时间:6.5 ns
备用内存宽度:9最大时钟频率 (fCLK):100 MHz
JESD-30 代码:S-PQFP-G80内存密度:36864 bit
内存集成电路类型:OTHER FIFO内存宽度:18
端子数量:80字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2KX18封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP80,.64SQ
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.015 A子类别:FIFOs
最大压摆率:0.035 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD
Base Number Matches:1

FQV243L10PFI 数据手册

 浏览型号FQV243L10PFI的Datasheet PDF文件第2页浏览型号FQV243L10PFI的Datasheet PDF文件第3页浏览型号FQV243L10PFI的Datasheet PDF文件第4页浏览型号FQV243L10PFI的Datasheet PDF文件第5页浏览型号FQV243L10PFI的Datasheet PDF文件第6页浏览型号FQV243L10PFI的Datasheet PDF文件第7页 
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
3.3 Volt Synchronous x9/x18 First-In/First-Out Queue  
Memory Organization  
262,144 x 18 / 524,288 x 9  
131,072 x 18 / 262,144 x 9  
65,536 x 18 / 131,072 x 9  
32,768 x 18 / 65,536 x 9  
Device  
FQV2113  
FQV2103  
FQV293  
FQV283  
Memory Organization  
16,384 x 18 / 32,768 x 9  
8,192 x 18 / 16,384 x 9  
4,096 x 18 / 8,192 x 9  
2,048 x 18 / 4,096 x 9  
Device  
FQV273  
FQV263  
FQV253  
FQV243  
Key Features  
Industry leading First-In/First-Out Queues (up to 166MHz)  
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)  
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)  
User selectable input and output port bus-sizing  
Big Endian/Little Endian user selectable byte representation  
3.3V power supply  
5V input tolerant on all control and data input pins  
5V output tolerant on all flags and data output pins  
Master Reset clears all previously programmed configurations including Write and Read pointers  
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations  
First Word Fall Through (FWFT) and Standard Timing modes  
Presets for eight different Almost Full and Almost Empty offset values  
Parallel/Serial programming of PRAF and PRAE offset values  
Programmable 8-bit or 9-bit parallel programming modes for offset values  
Full, Empty, Almost Full, Almost Empty, and Half Full indicators  
PRAF and PRAE operates in either synchronous or asynchronous modes  
Asynchronous output enable tri-state data output drivers  
Data retransmission with programmable zero or normal latency modes  
Available package: 80 - pin Plastic Thin Quad Flat Pack (TQFP)  
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above  
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above  
Product Description  
HBA’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory  
configurations (from 2,048 x 18 to 262,144 x 18 or 4,096 x 9 to 524,286 x 9). System designer has full flexibility of  
implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators  
allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial)  
indicators allow implementation of virtual queue depths.  
5V tolerant on all input and output pins allows easy interfacing with devices operating at higher voltage levels. Asynchronous  
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching  
capability.  
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and  
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will  
initialize Write and Read pointers to zero.  
In FWFT mode, the first data written into the queue appears on output data bus after the specified latency period at the low to  
high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when  
implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and  
EMPTY respectively.  
JANUARY 2003  
3F30918C  
Page 1 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  

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