5秒后页面跳转
捷配首页

Datasheet > FQV8070L10BBI
FQV8070L10BBI PDF预览

FQV8070L10BBI

更新时间： 2024-11-29 20:54:39
品牌 Logo 应用领域
联笙电子 - AMICC 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
51页 554K
描述
FIFO, 8KX80, 6.5ns, Synchronous, CMOS, PBGA256

阅读下载

中文翻译

获取价格

FQV8070L10BBI 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：BGA, BGA256,16X16,40Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.89最长访问时间：6.5 ns
最大时钟频率 (fCLK)：100 MHzJESD-30 代码：S-PBGA-B256
内存密度：655360 bit内存集成电路类型：OTHER FIFO
内存宽度：80端子数量：256
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：8KX80
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA256,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY电源：3.3 V
认证状态：Not Qualified最大待机电流：0.015 A
子类别：FIFOs最大压摆率：0.04 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

FQV8070L10BBI 数据手册

 浏览型号FQV8070L10BBI的Datasheet PDF文件第2页浏览型号FQV8070L10BBI的Datasheet PDF文件第3页浏览型号FQV8070L10BBI的Datasheet PDF文件第4页浏览型号FQV8070L10BBI的Datasheet PDF文件第5页浏览型号FQV8070L10BBI的Datasheet PDF文件第6页浏览型号FQV8070L10BBI的Datasheet PDF文件第7页 
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030  
FlexQ
TMIII Plus  
3.3 Volt Synchronous x 80 First-In/First-Out Queue  
Memory Configuration  
65,536 x 80  
Device  
FQV80100  
FQV8090  
FQV8080  
FQV8070  
Memory Configuration  
4,096 x 80  
Device  
FQV8060  
FQV8050  
FQV8040  
FQV8030  
32,768 x 80  
16,384 x 80  
8,192 x 80  
2,048 x 80  
1,024 x 80  
512 x 80  
Key Features  
•
Industry leading First-In/First-Out Queues (up to 166 MHz)  
•
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)  
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)  
User selectable input and output bus-sizing  
•
•
•
•
•
•
•
•
•
•
Big Endian/Little Endian user selectable byte representation  
3.3V power supply  
5V input tolerant on all control and data input pins  
5V output tolerant on all flags and data output pins  
Master Reset clears all previously programmed configurations including Write and Read pointers  
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations  
First Word Fall Through (FWFT) and Standard Timing modes  
Presets for eight different Almost Full and Almost Empty offset values  
•
•
•
Parallel/Serial programming of PRAF and PRAE offset values  
Programmable 8-bit or 10-bit parallel programming modes for offset values  
Full, Empty, Almost Full, Almost Empty, and Half Full indicators  
•
•
•
•
•
•
•
•
PRAF and PRAE operate in either synchronous or asynchronous modes  
Asynchronous output enable tri-state data output drivers  
Synchronous Read Chip Select  
Data retransmission with programmable zero or normal latency modes  
Boundary Scan (JTAG)  
Available package: 256 - pin Fine Pitch Ball Grid Array (BGA)  
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above  
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above  
Product Description  
HBA’s FlexQ™ III Plus offers industry leading FIFO queuing bandwidth (up to 12.0 Gbps) with a wide range of memory  
configurations (from 512 x 80 to 65,536 x 80). System designer has full flexibility of implementing deeper and wider queues  
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between  
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation  
of virtual queue depths.  
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous  
Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select is also available to  
control the state of data output drivers. Independent Write and Read controls provide rate-matching capability.  
Master Reset clears all previous programmed configurations by providing a low pulse on MRST pin. In addition, Write and  
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will  
initialize Write and Read pointers to zero.  
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high  
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing  
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.  
3F3P80D  
NOVEMBER 2002  
Page 1 of 51  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
1234567...51

中文翻译

下载PDF

与FQV8070L10BBI相关器件

型号 品牌 获取价格 描述 数据表
FQX-HQA-EVK-D0 TDK

获取价格

 		附件
FQY45N50F ETC

获取价格

 		TRANSISTOR | MOSFET | N-CHANNEL | 500V V(BR)DSS | 45A I(D) | TO-247VAR
FQZX363C15 CJ

获取价格

 		Zener Diode, 15V V(Z), 8%, 0.15W
FQZX363C5V6 CJ

获取价格

 		QUAD SURFACE MOUNT ZENER DIODE ARRAY
FQZX363C5V6-WBFBP-06C CJ

获取价格

 		QUAD SURFACE MOUNT ZENER DIODE ARRAY
FQZX363C6V8 CJ

获取价格

 		Zener Diode, 6.8V V(Z), 4.8%, 0.15W
FR 3.3V DIODES

获取价格

 		Fund Base, Phase Jitter < 1ps
FR 251 GOOD-ARK

获取价格

 		快恢复整流管
FR 252 GOOD-ARK

获取价格

 		快恢复整流管
FR 253 GOOD-ARK

获取价格

 		快恢复整流管

与FQV8070L10BBI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证