Datasheet > FQV80100L7.5BB

FQV80100L7.5BB

更新时间： 2024-09-25 20:37:07

品牌	Logo	应用领域
联笙电子 - AMICC		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
51页	522K
描述
FIFO, 64KX80, 5ns, Synchronous, CMOS, PBGA256

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技术参数
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FQV80100L7.5BB 技术参数

是否Rohs认证：	不符合	生命周期：	Contact Manufacturer
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.89
最长访问时间：	5 ns	最大时钟频率 (fCLK)：	133 MHz
JESD-30 代码：	S-PBGA-B256	内存密度：	5242880 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	80
端子数量：	256	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX80	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA256,16X16,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	3.3 V	认证状态：	Not Qualified
最大待机电流：	0.015 A	子类别：	FIFOs
最大压摆率：	0.04 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
Base Number Matches：	1

FQV80100L7.5BB 数据手册

FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030

FlexQ

^TMIII Plus

3.3 Volt Synchronous x 80 First-In/First-Out Queue

Memory Configuration

65,536 x 80

Device

FQV80100

FQV8090

FQV8080

FQV8070

Memory Configuration

4,096 x 80

Device

FQV8060

FQV8050

FQV8040

FQV8030

32,768 x 80

16,384 x 80

8,192 x 80

2,048 x 80

1,024 x 80

512 x 80

Key Features

•

Industry leading First-In/First-Out Queues (up to 166 MHz)

•

Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)

Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)

User selectable input and output bus-sizing

•

Big Endian/Little Endian user selectable byte representation

3.3V power supply

5V input tolerant on all control and data input pins

5V output tolerant on all flags and data output pins

Master Reset clears all previously programmed configurations including Write and Read pointers

Partial Reset clears Write and Read pointers but maintains all previously programmed configurations

First Word Fall Through (FWFT) and Standard Timing modes

Presets for eight different Almost Full and Almost Empty offset values

•

Parallel/Serial programming of PRAF and PRAE offset values

Programmable 8-bit or 10-bit parallel programming modes for offset values

Full, Empty, Almost Full, Almost Empty, and Half Full indicators

•

PRAF and PRAE operate in either synchronous or asynchronous modes

Asynchronous output enable tri-state data output drivers

Synchronous Read Chip Select

Data retransmission with programmable zero or normal latency modes

Boundary Scan (JTAG)

Available package: 256 - pin Fine Pitch Ball Grid Array (BGA)

(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above

(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above

Product Description

HBA’s FlexQ™ III Plus offers industry leading FIFO queuing bandwidth (up to 12.0 Gbps) with a wide range of memory

configurations (from 512 x 80 to 65,536 x 80). System designer has full flexibility of implementing deeper and wider queues

using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between

transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation

of virtual queue depths.

5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous

Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select is also available to

control the state of data output drivers. Independent Write and Read controls provide rate-matching capability.

Master Reset clears all previous programmed configurations by providing a low pulse on MRST pin. In addition, Write and

Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will

initialize Write and Read pointers to zero.

In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high

transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing

depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.

3F3P80D

NOVEMBER 2002

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与FQV80100L7.5BB相关器件

型号	品牌	获取价格	描述	数据表
FQV80100L7.5BBI	AMICC	获取价格	FIFO, 64KX80, 6.5ns, Synchronous, CMOS, PBGA256
FQV8070L10BB	AMICC	获取价格	FIFO, 8KX80, 6.5ns, Synchronous, CMOS, PBGA256
FQV8070L10BBI	AMICC	获取价格	FIFO, 8KX80, 6.5ns, Synchronous, CMOS, PBGA256
FQX-HQA-EVK-D0	TDK	获取价格	附件
FQY45N50F	ETC	获取价格	TRANSISTOR \| MOSFET \| N-CHANNEL \| 500V V(BR)DSS \| 45A I(D) \| TO-247VAR
FQZX363C15	CJ	获取价格	Zener Diode, 15V V(Z), 8%, 0.15W
FQZX363C5V6	CJ	获取价格	QUAD SURFACE MOUNT ZENER DIODE ARRAY
FQZX363C5V6-WBFBP-06C	CJ	获取价格	QUAD SURFACE MOUNT ZENER DIODE ARRAY
FQZX363C6V8	CJ	获取价格	Zener Diode, 6.8V V(Z), 4.8%, 0.15W
FR 3.3V	DIODES	获取价格	Fund Base, Phase Jitter < 1ps

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