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FQV291L7.5TF PDF预览

FQV291L7.5TF

更新时间: 2024-11-29 14:50:19
品牌 Logo 应用领域
联笙电子 - AMICC 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
33页 355K
描述
FIFO, 128KX9, 5ns, Synchronous, CMOS, PQFP64

FQV291L7.5TF 技术参数

是否Rohs认证:不符合生命周期:Contact Manufacturer
包装说明:QFP, QFP64,.47SQ,20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.89Is Samacsys:N
最长访问时间:5 ns最大时钟频率 (fCLK):133 MHz
JESD-30 代码:S-PQFP-G64内存密度:1179648 bit
内存集成电路类型:OTHER FIFO内存宽度:9
端子数量:64字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX9封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.02 A子类别:FIFOs
最大压摆率:0.055 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

FQV291L7.5TF 数据手册

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FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
3.3 Volt Synchronous x9 First-In/First-Out Queue  
Memory Configuration Part Number  
524,288 x 9  
262,144 x 9  
131,072 x 9  
65,536 x 9  
32,768 x 9  
16,384 x 9  
FQV2111  
FQV2101  
FQV291  
FQV281  
FQV271  
FQV261  
Key Features  
Industry leading First-In/First-Out Queues (up to 133MHz)  
Write cycle time of 7.5ns independent of Read cycle time  
Read cycle time of 7.5ns independent of Write cycle time  
User selectable input and output port bus-sizing  
Big Endian/Little Endian user selectable byte representation  
3.3V power supply  
5V input tolerant on all control and data input pins  
5V output tolerant on all flags and data output pins  
Master Reset clears all previously programmed configurations including Write and Read pointers.  
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations.  
First Word Fall Through (FWFT) and Standard Timing modes  
Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values  
Parallel/Serial programming of PRAF and PRAE offset values  
Full, Empty, Almost Full, Almost Empty and Half Full indicators  
Asynchronous output enable tri-state data output drivers  
Data retransmission  
Available package: 64 - pin Plastic Thin Quad Flat Pack (TQFP), 64 – pin Slim Thin Quad Flat Pack (STQFP)  
(0°C to 70°C) Commercial operating temperature available for cycle time of 7.5ns and above  
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above  
Product Description  
HBA’s FlexQ™ II offers industry leading FIFO queuing bandwidth (up to 1.5 Gbps) with a wide range of memory  
configurations (from 16,384 x 9 to 524,288 x 9). System designer has full flexibility of implementing deeper and wider queues  
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between  
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation  
of virtual queue depths.  
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous  
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching  
capability.  
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and  
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will  
initialize Write and Read pointers to zero.  
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high  
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing  
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.  
In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and QRDY  
respectively.  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 1 of 1  

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