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FMS7950KWC PDF预览

FMS7950KWC

更新时间: 2024-02-22 16:48:25
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 时钟外围集成电路晶体
页数 文件大小 规格书
9页 69K
描述
Clock Generator, 175MHz, CMOS, PQFP32, LQFP-32

FMS7950KWC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:unknown风险等级:5.88
Is Samacsys:NJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
湿度敏感等级:NOT SPECIFIED端子数量:32
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:175 MHz封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:43 MHz认证状态:COMMERCIAL
座面最大高度:1.6 mm最大供电电压:3.5 V
最小供电电压:3.1 V标称供电电压:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

FMS7950KWC 数据手册

 浏览型号FMS7950KWC的Datasheet PDF文件第2页浏览型号FMS7950KWC的Datasheet PDF文件第3页浏览型号FMS7950KWC的Datasheet PDF文件第4页浏览型号FMS7950KWC的Datasheet PDF文件第5页浏览型号FMS7950KWC的Datasheet PDF文件第6页浏览型号FMS7950KWC的Datasheet PDF文件第7页 
www.fairchildsemi.com  
FMS7950  
Clock Multiplier  
Feedback select (FBsel) pin allows for wider range of input  
frequencies. When connected low, the lower input frequency  
range is selected. This provides output frequencies of up to  
eight times the input (see table 3). The higher input range is  
allowed when FBsel is connected high.  
Features  
• Crystal reference input  
• Up to 175 MHz of output frequency  
• Nine configurable outputs  
• Output enable pin  
• 250 pS of output to output skew  
• 300 pS of Cycle to Cycle Jitter  
• VDD Range of 3.3V 0.2V  
• Commercial temperature range  
• Available in 32 pin LQFP  
There are four banks of outputs where each bank has a dedi-  
cated divide select (DIV_SEL). Depending on the divide  
selection, the outputs are one half, one quarter, or one eighth  
of the VCO speed (see table 2 for details).  
REF_SEL allows selection between crystal input or a clock  
driven input. Connecting PLL_EN LOW and REF_SEL  
HIGH will disable the Phase locked loop when the crystal  
oscillator is not used. In this mode, FMS7950 will be in  
clock buffer mode where any clock applied to TCLK will be  
divided down to the four output banks per Table 2. This is  
ideal for system diagnostic test.  
Description  
FMS7950 is a high speed clock synthesizer designed for clock  
multiplication applications. It uses phase locked loop technol-  
ogy to generate frequencies up to 175 MHz. It has four banks  
of configurable outputs.  
FMS7950 operates at 3.3 Volts and is available in 32 pin LQFP.  
Block Diagram  
REF_SEL  
PLL_EN  
OE  
TCLK  
QA  
QB  
MUX  
MUX  
PLL  
X1  
X2  
XTAL  
OSC  
QC0  
QC1  
QD0  
QD1  
QD2  
FBsel  
DIV_SEL A  
DIV_SEL B  
DIV_SEL C  
Control  
Logic  
QD3  
QD4  
DIV_SEL D  
REV. 1.0.0 1/9/01  

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