FMS7951

更新时间： 2024-11-20 04:18:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		时钟
页数	文件大小	规格书
8页	70K
描述
Zero Delay Clock Multiplier

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FMS7951 数据手册

www.fairchildsemi.com

FMS7951

Zero Delay Clock Multiplier

It has four banks of conﬁgurable outputs. By externally con-

necting one of the outputs to FBIN, the internal PLL will

lock in both phase and frequency to the incoming clock. Any

changes to the input clock will be tracked by the outputs.

Depending on the selected output for feedback connection,

the output frequencies will be as 1X, 2X or 4X of the input.

Features

• Low Voltage CMOS or PECL reference input

• Up to 175 MHz of output frequency

• Nine conﬁgurable outputs

• Output enable pin

• 250 pS of output to output skew

• 300 pS of Cycle to Cycle Jitter

• V_DDRange of 3.3V 0.2V

• Commercial temperature range

• Available in 32 pin TQFP

REF_SEL allows selection between PECL input or TCLK a

CMOS clock driven input. Connecting PLL_EN LOW and

REF_SEL HIGH will by pass the Phase locked loop. In this

mode, FMS7951 will be in clock buffer mode where any

clock applied to TCLK will be divided down to the four out-

put banks. This is ideal for system diagnostic test. When

PLL_EN is HIGH, the PLL is enabled, and any clock applied

to TCLK will be locked in both phase and frequency to

FBIN. PECL_CLK is activated when REF_SEL is high.

Description

FMS7951 is a high speed, zero delay, low skew clock driver. It

uses phase locked loop technology to generate frequencies up

to 175 MHz.

FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP.

Block Diagram

REF_SEL

PLL_EN

TCLK

MUX

PECL_CLK

PLL

QC0

FBIN

QC1

QD0

QD1

QD2

DIV_SEL A

DIV_SEL B

DIV_SEL C

Control

Logic

QD3

QD4

DIV_SEL D

REV. 1.0.0 1/9/01

12 3 4 5 6 7 8

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